![Linus Torvalds](/assets/img/avatar_default.png)
- Generic execve, kernel_thread, fork/vfork/clone. - Preparatory patches for KVM support (initialising EL2 mode for later installing KVM support, hypervisor stub). - Signal handling corner case fix (alternative signal stack set up for a SEGV handler, which is raised in response to RLIMIT_STACK being reached). - Sub-nanosecond timer error fix. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iQIcBAABAgAGBQJQx1TPAAoJEGvWsS0AyF7xSrEP/R7KPhKSKIJKW0n3nP/uGe5g isUiTM+y4koGzeHShao8I7VUXZLJptYHiviy12Rf0S/IK0L25P1p29ABLndd8SPB 5lqQehLz35bAIzmRXypvz4szpCwlRXPzEcHX7cnid0Nv27A9hVpfssYM2HIKLIJN 1AXZAxjlNmPHCc+hd+QOnP8d7h6KGiZWqiC1lsuU12Ma4oZIwiS225oxUdMg5d4I AxfWAvVLy14eNxDRqBgA0W2Jxe62TD82LrgD4tP88mbwWsFIyE5dea2yYShOJnBe mwLWw4Jovfe5VLSn00yggqM5JPp36sM/7Bka5EZaGKY2HllVtSwqnshUChG3fw3/ fepN4nB0L8lPgTMfQAUjNKqZWgt2vwIGC+7GLX+Sg6/kOidRaxsQgU710gNvceZu E417RTtW4WM8IA+euCTiq3huJt7iOt8APSblpPWnrf8M7ntJKV4ESTOhtN30mR2D ZYeMZp1DYrET3Pxkd+bMdaRYGhMqAlpfCF096H+A4FscicbDLC+KincWtW/YpOXE voWDxE/Rd+3nAhCVL+A2HUSw9lNddsFvxRR9hQWfQ3uvMiDp7AS6O4EAYcK60GiA YsEnksMQr/ksscNf/7nvpY6DBNkeuZjj9IGfbFYVqWZ80f//8NEoJCNDzNPlATHU ddPpD5ZayUQ3UUMulQGg =fQ+2 -----END PGP SIGNATURE----- Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 Pull ARM64 updates from Catalin Marinas: - Generic execve, kernel_thread, fork/vfork/clone. - Preparatory patches for KVM support (initialising EL2 mode for later installing KVM support, hypervisor stub). - Signal handling corner case fix (alternative signal stack set up for a SEGV handler, which is raised in response to RLIMIT_STACK being reached). - Sub-nanosecond timer error fix. * tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: (30 commits) arm64: Update the MAINTAINERS entry arm64: compat for clock_adjtime(2) is miswired arm64: move FP-SIMD save/restore code to a macro arm64: hyp: initialize vttbr_el2 to zero arm64: add hypervisor stub arm64: record boot mode when entering the kernel arm64: move vector entry macro to assembler.h arm64: add AArch32 execution modes to ptrace.h arm64: expand register mapping between AArch32 and AArch64 arm64: generic timer: use virtual counter instead of physical at EL0 arm64: vdso: defer shifting of nanosecond component of timespec arm64: vdso: rework __do_get_tspec register allocation and return shift arm64: vdso: check sequence counter even for coarse realtime operations arm64: vdso: fix clocksource mask when extracting bottom 56 bits ARM64: Remove incorrect Kconfig symbol HAVE_SPARSE_IRQ Documentation: Fixes a word in Documentation/arm64/memory.txt arm64: Make !dirty ptes read-only arm64: Convert empty flush_cache_{mm,page} functions to static inline arm64: signal: let the compiler inline compat_get_sigframe arm64: signal: return struct rt_sigframe from get_sigframe ... Conflicts: arch/arm64/include/asm/unistd32.h
233 lines
5.9 KiB
C
233 lines
5.9 KiB
C
/*
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* Generic timers support
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/cpu.h>
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#include <linux/jiffies.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <clocksource/arm_generic.h>
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#include <asm/arm_generic.h>
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static u32 arch_timer_rate;
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static u64 sched_clock_mult __read_mostly;
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static DEFINE_PER_CPU(struct clock_event_device, arch_timer_evt);
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static int arch_timer_ppi;
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static irqreturn_t arch_timer_handle_irq(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
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if (ctrl & ARCH_TIMER_CTRL_ISTATUS) {
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ctrl |= ARCH_TIMER_CTRL_IMASK;
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arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static void arch_timer_stop(void)
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{
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
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ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
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arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
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}
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static void arch_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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arch_timer_stop();
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break;
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default:
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break;
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}
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}
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static int arch_timer_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
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ctrl |= ARCH_TIMER_CTRL_ENABLE;
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ctrl &= ~ARCH_TIMER_CTRL_IMASK;
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arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
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arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
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return 0;
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}
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static void __cpuinit arch_timer_setup(struct clock_event_device *clk)
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{
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/* Let's make sure the timer is off before doing anything else */
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arch_timer_stop();
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clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
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clk->name = "arch_sys_timer";
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clk->rating = 400;
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clk->set_mode = arch_timer_set_mode;
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clk->set_next_event = arch_timer_set_next_event;
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clk->irq = arch_timer_ppi;
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clk->cpumask = cpumask_of(smp_processor_id());
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clockevents_config_and_register(clk, arch_timer_rate,
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0xf, 0x7fffffff);
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enable_percpu_irq(clk->irq, 0);
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/* Ensure the virtual counter is visible to userspace for the vDSO. */
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arch_counter_enable_user_access();
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}
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static void __init arch_timer_calibrate(void)
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{
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if (arch_timer_rate == 0) {
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arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
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arch_timer_rate = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
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/* Check the timer frequency. */
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if (arch_timer_rate == 0)
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panic("Architected timer frequency is set to zero.\n"
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"You must set this in your .dts file\n");
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}
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/* Cache the sched_clock multiplier to save a divide in the hot path. */
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sched_clock_mult = DIV_ROUND_CLOSEST(NSEC_PER_SEC, arch_timer_rate);
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pr_info("Architected local timer running at %u.%02uMHz.\n",
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arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
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}
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static cycle_t arch_counter_read(struct clocksource *cs)
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{
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return arch_counter_get_cntpct();
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}
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static struct clocksource clocksource_counter = {
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.name = "arch_sys_counter",
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.rating = 400,
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.read = arch_counter_read,
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.mask = CLOCKSOURCE_MASK(56),
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.flags = (CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_VALID_FOR_HRES),
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};
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int read_current_timer(unsigned long *timer_value)
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{
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*timer_value = arch_counter_get_cntpct();
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return 0;
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}
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unsigned long long notrace sched_clock(void)
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{
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return arch_counter_get_cntvct() * sched_clock_mult;
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}
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static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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int cpu = (long)hcpu;
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struct clock_event_device *clk = per_cpu_ptr(&arch_timer_evt, cpu);
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switch(action) {
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case CPU_STARTING:
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case CPU_STARTING_FROZEN:
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arch_timer_setup(clk);
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break;
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case CPU_DYING:
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case CPU_DYING_FROZEN:
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pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
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clk->irq, cpu);
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disable_percpu_irq(clk->irq);
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arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block __cpuinitdata arch_timer_cpu_nb = {
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.notifier_call = arch_timer_cpu_notify,
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};
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static const struct of_device_id arch_timer_of_match[] __initconst = {
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{ .compatible = "arm,armv8-timer" },
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{},
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};
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int __init arm_generic_timer_init(void)
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{
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struct device_node *np;
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int err;
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u32 freq;
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np = of_find_matching_node(NULL, arch_timer_of_match);
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if (!np) {
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pr_err("arch_timer: can't find DT node\n");
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return -ENODEV;
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}
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/* Try to determine the frequency from the device tree or CNTFRQ */
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if (!of_property_read_u32(np, "clock-frequency", &freq))
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arch_timer_rate = freq;
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arch_timer_calibrate();
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arch_timer_ppi = irq_of_parse_and_map(np, 0);
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pr_info("arch_timer: found %s irq %d\n", np->name, arch_timer_ppi);
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err = request_percpu_irq(arch_timer_ppi, arch_timer_handle_irq,
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np->name, &arch_timer_evt);
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if (err) {
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pr_err("arch_timer: can't register interrupt %d (%d)\n",
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arch_timer_ppi, err);
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return err;
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}
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clocksource_register_hz(&clocksource_counter, arch_timer_rate);
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/* Calibrate the delay loop directly */
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lpj_fine = DIV_ROUND_CLOSEST(arch_timer_rate, HZ);
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/* Immediately configure the timer on the boot CPU */
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arch_timer_setup(this_cpu_ptr(&arch_timer_evt));
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register_cpu_notifier(&arch_timer_cpu_nb);
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return 0;
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}
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