![Linus Torvalds](/assets/img/avatar_default.png)
- arm64 support for syscall emulation via PTRACE_SYSEMU{,_SINGLESTEP} - Wire up VM_FLUSH_RESET_PERMS for arm64, allowing the core code to manage the permissions of executable vmalloc regions more strictly - Slight performance improvement by keeping softirqs enabled while touching the FPSIMD/SVE state (kernel_neon_begin/end) - Expose a couple of ARMv8.5 features to user (HWCAP): CondM (new XAFLAG and AXFLAG instructions for floating point comparison flags manipulation) and FRINT (rounding floating point numbers to integers) - Re-instate ARM64_PSEUDO_NMI support which was previously marked as BROKEN due to some bugs (now fixed) - Improve parking of stopped CPUs and implement an arm64-specific panic_smp_self_stop() to avoid warning on not being able to stop secondary CPUs during panic - perf: enable the ARM Statistical Profiling Extensions (SPE) on ACPI platforms - perf: DDR performance monitor support for iMX8QXP - cache_line_size() can now be set from DT or ACPI/PPTT if provided to cope with a system cache info not exposed via the CPUID registers - Avoid warning on hardware cache line size greater than ARCH_DMA_MINALIGN if the system is fully coherent - arm64 do_page_fault() and hugetlb cleanups - Refactor set_pte_at() to avoid redundant READ_ONCE(*ptep) - Ignore ACPI 5.1 FADTs reported as 5.0 (infer from the 'arm_boot_flags' introduced in 5.1) - CONFIG_RANDOMIZE_BASE now enabled in defconfig - Allow the selection of ARM64_MODULE_PLTS, currently only done via RANDOMIZE_BASE (and an erratum workaround), allowing modules to spill over into the vmalloc area - Make ZONE_DMA32 configurable -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAl0eHqcACgkQa9axLQDI XvFyNA/+L+bnkz8m3ncydlqqfXomQn4eJJVQ8Uksb0knJz+1+3CUxxbO4ry4jXZN fMkbggYrDPRKpDbsUl0lsRipj7jW9bqan+N37c3SWqCkgb6HqDaHViwxdx6Ec/Uk gHudozDSPh/8c7hxGcSyt/CFyuW6b+8eYIQU5rtIgz8aVY2BypBvS/7YtYCbIkx0 w4CFleRTK1zXD5mJQhrc6jyDx659sVkrAvdhf6YIymOY8nBTv40vwdNo3beJMYp8 Po/+0Ixu+VkHUNtmYYZQgP/AGH96xiTcRnUqd172JdtRPpCLqnLqwFokXeVIlUKT KZFMDPzK+756Ayn4z4huEePPAOGlHbJje8JVNnFyreKhVVcCotW7YPY/oJR10bnc eo7yD+DxABTn+93G2yP436bNVa8qO1UqjOBfInWBtnNFJfANIkZweij/MQ6MjaTA o7KtviHnZFClefMPoiI7HDzwL8XSmsBDbeQ04s2Wxku1Y2xUHLx4iLmadwLQ1ZPb lZMTZP3N/T1554MoURVA1afCjAwiqU3bt1xDUGjbBVjLfSPBAn/25IacsG9Li9AF 7Rp1M9VhrfLftjFFkB2HwpbhRASOxaOSx+EI3kzEfCtM2O9I1WHgP3rvCdc3l0HU tbK0/IggQicNgz7GSZ8xDlWPwwSadXYGLys+xlMZEYd3pDIOiFc= =0TDT -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: - arm64 support for syscall emulation via PTRACE_SYSEMU{,_SINGLESTEP} - Wire up VM_FLUSH_RESET_PERMS for arm64, allowing the core code to manage the permissions of executable vmalloc regions more strictly - Slight performance improvement by keeping softirqs enabled while touching the FPSIMD/SVE state (kernel_neon_begin/end) - Expose a couple of ARMv8.5 features to user (HWCAP): CondM (new XAFLAG and AXFLAG instructions for floating point comparison flags manipulation) and FRINT (rounding floating point numbers to integers) - Re-instate ARM64_PSEUDO_NMI support which was previously marked as BROKEN due to some bugs (now fixed) - Improve parking of stopped CPUs and implement an arm64-specific panic_smp_self_stop() to avoid warning on not being able to stop secondary CPUs during panic - perf: enable the ARM Statistical Profiling Extensions (SPE) on ACPI platforms - perf: DDR performance monitor support for iMX8QXP - cache_line_size() can now be set from DT or ACPI/PPTT if provided to cope with a system cache info not exposed via the CPUID registers - Avoid warning on hardware cache line size greater than ARCH_DMA_MINALIGN if the system is fully coherent - arm64 do_page_fault() and hugetlb cleanups - Refactor set_pte_at() to avoid redundant READ_ONCE(*ptep) - Ignore ACPI 5.1 FADTs reported as 5.0 (infer from the 'arm_boot_flags' introduced in 5.1) - CONFIG_RANDOMIZE_BASE now enabled in defconfig - Allow the selection of ARM64_MODULE_PLTS, currently only done via RANDOMIZE_BASE (and an erratum workaround), allowing modules to spill over into the vmalloc area - Make ZONE_DMA32 configurable * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (54 commits) perf: arm_spe: Enable ACPI/Platform automatic module loading arm_pmu: acpi: spe: Add initial MADT/SPE probing ACPI/PPTT: Add function to return ACPI 6.3 Identical tokens ACPI/PPTT: Modify node flag detection to find last IDENTICAL x86/entry: Simplify _TIF_SYSCALL_EMU handling arm64: rename dump_instr as dump_kernel_instr arm64/mm: Drop [PTE|PMD]_TYPE_FAULT arm64: Implement panic_smp_self_stop() arm64: Improve parking of stopped CPUs arm64: Expose FRINT capabilities to userspace arm64: Expose ARMv8.5 CondM capability to userspace arm64: defconfig: enable CONFIG_RANDOMIZE_BASE arm64: ARM64_MODULES_PLTS must depend on MODULES arm64: bpf: do not allocate executable memory arm64/kprobes: set VM_FLUSH_RESET_PERMS on kprobe instruction pages arm64/mm: wire up CONFIG_ARCH_HAS_SET_DIRECT_MAP arm64: module: create module allocations without exec permissions arm64: Allow user selection of ARM64_MODULE_PLTS acpi/arm64: ignore 5.1 FADTs that are reported as 5.0 arm64: Allow selecting Pseudo-NMI again ...
399 lines
9.7 KiB
C
399 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Record and handle CPU attributes.
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*
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* Copyright (C) 2014 ARM Ltd.
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*/
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#include <asm/arch_timer.h>
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#include <asm/cache.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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#include <asm/fpsimd.h>
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/compat.h>
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#include <linux/elf.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/personality.h>
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#include <linux/preempt.h>
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#include <linux/printk.h>
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#include <linux/seq_file.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/delay.h>
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/*
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* In case the boot CPU is hotpluggable, we record its initial state and
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* current state separately. Certain system registers may contain different
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* values depending on configuration at or after reset.
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*/
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DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
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static struct cpuinfo_arm64 boot_cpu_data;
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static char *icache_policy_str[] = {
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[0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN",
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[ICACHE_POLICY_VIPT] = "VIPT",
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[ICACHE_POLICY_PIPT] = "PIPT",
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[ICACHE_POLICY_VPIPT] = "VPIPT",
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};
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unsigned long __icache_flags;
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static const char *const hwcap_str[] = {
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"fp",
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"asimd",
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"evtstrm",
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"aes",
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"pmull",
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"sha1",
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"sha2",
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"crc32",
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"atomics",
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"fphp",
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"asimdhp",
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"cpuid",
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"asimdrdm",
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"jscvt",
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"fcma",
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"lrcpc",
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"dcpop",
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"sha3",
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"sm3",
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"sm4",
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"asimddp",
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"sha512",
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"sve",
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"asimdfhm",
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"dit",
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"uscat",
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"ilrcpc",
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"flagm",
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"ssbs",
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"sb",
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"paca",
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"pacg",
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"dcpodp",
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"sve2",
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"sveaes",
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"svepmull",
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"svebitperm",
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"svesha3",
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"svesm4",
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"flagm2",
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"frint",
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NULL
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};
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#ifdef CONFIG_COMPAT
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static const char *const compat_hwcap_str[] = {
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"swp",
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"half",
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"thumb",
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"26bit",
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"fastmult",
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"fpa",
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"vfp",
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"edsp",
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"java",
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"iwmmxt",
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"crunch",
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"thumbee",
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"neon",
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"vfpv3",
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"vfpv3d16",
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"tls",
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"vfpv4",
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"idiva",
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"idivt",
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"vfpd32",
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"lpae",
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"evtstrm",
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NULL
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};
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static const char *const compat_hwcap2_str[] = {
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"aes",
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"pmull",
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"sha1",
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"sha2",
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"crc32",
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NULL
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};
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#endif /* CONFIG_COMPAT */
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static int c_show(struct seq_file *m, void *v)
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{
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int i, j;
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bool compat = personality(current->personality) == PER_LINUX32;
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for_each_online_cpu(i) {
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struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
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u32 midr = cpuinfo->reg_midr;
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/*
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* glibc reads /proc/cpuinfo to determine the number of
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* online processors, looking for lines beginning with
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* "processor". Give glibc what it expects.
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*/
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seq_printf(m, "processor\t: %d\n", i);
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if (compat)
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seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
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MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
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seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
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loops_per_jiffy / (500000UL/HZ),
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loops_per_jiffy / (5000UL/HZ) % 100);
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/*
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* Dump out the common processor features in a single line.
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* Userspace should read the hwcaps with getauxval(AT_HWCAP)
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* rather than attempting to parse this, but there's a body of
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* software which does already (at least for 32-bit).
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*/
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seq_puts(m, "Features\t:");
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if (compat) {
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#ifdef CONFIG_COMPAT
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for (j = 0; compat_hwcap_str[j]; j++)
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if (compat_elf_hwcap & (1 << j))
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seq_printf(m, " %s", compat_hwcap_str[j]);
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for (j = 0; compat_hwcap2_str[j]; j++)
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if (compat_elf_hwcap2 & (1 << j))
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seq_printf(m, " %s", compat_hwcap2_str[j]);
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#endif /* CONFIG_COMPAT */
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} else {
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for (j = 0; hwcap_str[j]; j++)
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if (cpu_have_feature(j))
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seq_printf(m, " %s", hwcap_str[j]);
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}
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seq_puts(m, "\n");
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seq_printf(m, "CPU implementer\t: 0x%02x\n",
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MIDR_IMPLEMENTOR(midr));
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seq_printf(m, "CPU architecture: 8\n");
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seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
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seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
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seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
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}
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return 0;
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}
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static void *c_start(struct seq_file *m, loff_t *pos)
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{
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return *pos < 1 ? (void *)1 : NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t *pos)
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{
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++*pos;
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return NULL;
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}
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static void c_stop(struct seq_file *m, void *v)
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{
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}
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const struct seq_operations cpuinfo_op = {
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.start = c_start,
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.next = c_next,
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.stop = c_stop,
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.show = c_show
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};
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static struct kobj_type cpuregs_kobj_type = {
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.sysfs_ops = &kobj_sysfs_ops,
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};
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/*
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* The ARM ARM uses the phrase "32-bit register" to describe a register
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* whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
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* no statement is made as to whether the upper 32 bits will or will not
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* be made use of in future, and between ARM DDI 0487A.c and ARM DDI
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* 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
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*
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* Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
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* registers, we expose them both as 64 bit values to cater for possible
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* future expansion without an ABI break.
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*/
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#define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
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#define CPUREGS_ATTR_RO(_name, _field) \
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static ssize_t _name##_show(struct kobject *kobj, \
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struct kobj_attribute *attr, char *buf) \
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{ \
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struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
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\
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if (info->reg_midr) \
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return sprintf(buf, "0x%016x\n", info->reg_##_field); \
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else \
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return 0; \
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} \
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static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
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CPUREGS_ATTR_RO(midr_el1, midr);
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CPUREGS_ATTR_RO(revidr_el1, revidr);
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static struct attribute *cpuregs_id_attrs[] = {
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&cpuregs_attr_midr_el1.attr,
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&cpuregs_attr_revidr_el1.attr,
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NULL
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};
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static const struct attribute_group cpuregs_attr_group = {
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.attrs = cpuregs_id_attrs,
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.name = "identification"
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};
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static int cpuid_cpu_online(unsigned int cpu)
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{
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int rc;
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struct device *dev;
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struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
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dev = get_cpu_device(cpu);
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if (!dev) {
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rc = -ENODEV;
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goto out;
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}
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rc = kobject_add(&info->kobj, &dev->kobj, "regs");
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if (rc)
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goto out;
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rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
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if (rc)
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kobject_del(&info->kobj);
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out:
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return rc;
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}
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static int cpuid_cpu_offline(unsigned int cpu)
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{
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struct device *dev;
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struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
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dev = get_cpu_device(cpu);
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if (!dev)
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return -ENODEV;
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if (info->kobj.parent) {
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sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
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kobject_del(&info->kobj);
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}
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return 0;
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}
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static int __init cpuinfo_regs_init(void)
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{
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int cpu, ret;
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for_each_possible_cpu(cpu) {
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struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
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kobject_init(&info->kobj, &cpuregs_kobj_type);
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}
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ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
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cpuid_cpu_online, cpuid_cpu_offline);
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if (ret < 0) {
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pr_err("cpuinfo: failed to register hotplug callbacks.\n");
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return ret;
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}
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return 0;
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}
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static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
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{
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unsigned int cpu = smp_processor_id();
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u32 l1ip = CTR_L1IP(info->reg_ctr);
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switch (l1ip) {
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case ICACHE_POLICY_PIPT:
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break;
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case ICACHE_POLICY_VPIPT:
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set_bit(ICACHEF_VPIPT, &__icache_flags);
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break;
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default:
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/* Fallthrough */
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case ICACHE_POLICY_VIPT:
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/* Assume aliasing */
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set_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
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}
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static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
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{
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info->reg_cntfrq = arch_timer_get_cntfrq();
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/*
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* Use the effective value of the CTR_EL0 than the raw value
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* exposed by the CPU. CTR_E0.IDC field value must be interpreted
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* with the CLIDR_EL1 fields to avoid triggering false warnings
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* when there is a mismatch across the CPUs. Keep track of the
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* effective value of the CTR_EL0 in our internal records for
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* acurate sanity check and feature enablement.
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*/
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info->reg_ctr = read_cpuid_effective_cachetype();
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info->reg_dczid = read_cpuid(DCZID_EL0);
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info->reg_midr = read_cpuid_id();
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info->reg_revidr = read_cpuid(REVIDR_EL1);
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info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
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info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
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info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
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info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
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info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
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info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
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info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
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info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
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info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
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info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
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/* Update the 32bit ID registers only if AArch32 is implemented */
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if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
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info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
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info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
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info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
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info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
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info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
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info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
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info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
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info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
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info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
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info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
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info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
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info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
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info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
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info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
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info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
|
|
info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_ARM64_SVE) &&
|
|
id_aa64pfr0_sve(info->reg_id_aa64pfr0))
|
|
info->reg_zcr = read_zcr_features();
|
|
|
|
cpuinfo_detect_icache_policy(info);
|
|
}
|
|
|
|
void cpuinfo_store_cpu(void)
|
|
{
|
|
struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
|
|
__cpuinfo_store_cpu(info);
|
|
update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
|
|
}
|
|
|
|
void __init cpuinfo_store_boot_cpu(void)
|
|
{
|
|
struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
|
|
__cpuinfo_store_cpu(info);
|
|
|
|
boot_cpu_data = *info;
|
|
init_cpu_features(&boot_cpu_data);
|
|
}
|
|
|
|
device_initcall(cpuinfo_regs_init);
|