![Marc Zyngier](/assets/img/avatar_default.png)
On a CPU that doesn't support SSBS, PSTATE[12] is RES0. In a system
where only some of the CPUs implement SSBS, we end-up losing track of
the SSBS bit across task migration.
To address this issue, let's force the SSBS bit on context switch.
Fixes: 8f04e8e6e2
("arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3")
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[will: inverted logic and added comments]
Signed-off-by: Will Deacon <will@kernel.org>
568 lines
14 KiB
C
568 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Based on arch/arm/kernel/process.c
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*
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* Original Copyright (C) 1995 Linus Torvalds
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* Copyright (C) 1996-2000 Russell King - Converted to ARM.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#include <stdarg.h>
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#include <linux/compat.h>
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#include <linux/efi.h>
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <linux/sched/debug.h>
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#include <linux/sched/task.h>
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#include <linux/sched/task_stack.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/user.h>
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#include <linux/delay.h>
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#include <linux/reboot.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <linux/elfcore.h>
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#include <linux/pm.h>
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#include <linux/tick.h>
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#include <linux/utsname.h>
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#include <linux/uaccess.h>
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#include <linux/random.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/personality.h>
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#include <linux/notifier.h>
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#include <trace/events/power.h>
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#include <linux/percpu.h>
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#include <linux/thread_info.h>
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#include <asm/alternative.h>
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#include <asm/arch_gicv3.h>
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#include <asm/compat.h>
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#include <asm/cacheflush.h>
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#include <asm/exec.h>
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#include <asm/fpsimd.h>
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#include <asm/mmu_context.h>
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#include <asm/processor.h>
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#include <asm/pointer_auth.h>
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#include <asm/stacktrace.h>
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#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
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#include <linux/stackprotector.h>
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unsigned long __stack_chk_guard __read_mostly;
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EXPORT_SYMBOL(__stack_chk_guard);
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#endif
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/*
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* Function pointers to optional machine specific functions
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*/
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void (*pm_power_off)(void);
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EXPORT_SYMBOL_GPL(pm_power_off);
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void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
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static void __cpu_do_idle(void)
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{
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dsb(sy);
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wfi();
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}
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static void __cpu_do_idle_irqprio(void)
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{
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unsigned long pmr;
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unsigned long daif_bits;
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daif_bits = read_sysreg(daif);
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write_sysreg(daif_bits | PSR_I_BIT, daif);
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/*
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* Unmask PMR before going idle to make sure interrupts can
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* be raised.
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*/
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pmr = gic_read_pmr();
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gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
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__cpu_do_idle();
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gic_write_pmr(pmr);
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write_sysreg(daif_bits, daif);
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}
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/*
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* cpu_do_idle()
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*
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* Idle the processor (wait for interrupt).
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*
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* If the CPU supports priority masking we must do additional work to
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* ensure that interrupts are not masked at the PMR (because the core will
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* not wake up if we block the wake up signal in the interrupt controller).
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*/
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void cpu_do_idle(void)
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{
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if (system_uses_irq_prio_masking())
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__cpu_do_idle_irqprio();
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else
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__cpu_do_idle();
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}
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/*
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* This is our default idle handler.
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*/
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void arch_cpu_idle(void)
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{
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/*
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* This should do all the clock switching and wait for interrupt
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* tricks
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*/
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trace_cpu_idle_rcuidle(1, smp_processor_id());
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cpu_do_idle();
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local_irq_enable();
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trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
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}
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#ifdef CONFIG_HOTPLUG_CPU
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void arch_cpu_idle_dead(void)
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{
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cpu_die();
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}
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#endif
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/*
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* Called by kexec, immediately prior to machine_kexec().
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*
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* This must completely disable all secondary CPUs; simply causing those CPUs
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* to execute e.g. a RAM-based pin loop is not sufficient. This allows the
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* kexec'd kernel to use any and all RAM as it sees fit, without having to
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* avoid any code or data used by any SW CPU pin loop. The CPU hotplug
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* functionality embodied in disable_nonboot_cpus() to achieve this.
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*/
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void machine_shutdown(void)
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{
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disable_nonboot_cpus();
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}
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/*
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* Halting simply requires that the secondary CPUs stop performing any
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* activity (executing tasks, handling interrupts). smp_send_stop()
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* achieves this.
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*/
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void machine_halt(void)
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{
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local_irq_disable();
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smp_send_stop();
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while (1);
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}
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/*
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* Power-off simply requires that the secondary CPUs stop performing any
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* activity (executing tasks, handling interrupts). smp_send_stop()
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* achieves this. When the system power is turned off, it will take all CPUs
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* with it.
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*/
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void machine_power_off(void)
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{
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local_irq_disable();
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smp_send_stop();
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if (pm_power_off)
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pm_power_off();
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}
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/*
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* Restart requires that the secondary CPUs stop performing any activity
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* while the primary CPU resets the system. Systems with multiple CPUs must
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* provide a HW restart implementation, to ensure that all CPUs reset at once.
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* This is required so that any code running after reset on the primary CPU
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* doesn't have to co-ordinate with other CPUs to ensure they aren't still
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* executing pre-reset code, and using RAM that the primary CPU's code wishes
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* to use. Implementing such co-ordination would be essentially impossible.
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*/
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void machine_restart(char *cmd)
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{
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/* Disable interrupts first */
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local_irq_disable();
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smp_send_stop();
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/*
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* UpdateCapsule() depends on the system being reset via
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* ResetSystem().
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*/
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if (efi_enabled(EFI_RUNTIME_SERVICES))
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efi_reboot(reboot_mode, NULL);
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/* Now call the architecture specific reboot code. */
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if (arm_pm_restart)
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arm_pm_restart(reboot_mode, cmd);
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else
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do_kernel_restart(cmd);
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/*
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* Whoops - the architecture was unable to reboot.
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*/
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printk("Reboot failed -- System halted\n");
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while (1);
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}
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static void print_pstate(struct pt_regs *regs)
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{
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u64 pstate = regs->pstate;
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if (compat_user_mode(regs)) {
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printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c)\n",
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pstate,
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pstate & PSR_AA32_N_BIT ? 'N' : 'n',
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pstate & PSR_AA32_Z_BIT ? 'Z' : 'z',
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pstate & PSR_AA32_C_BIT ? 'C' : 'c',
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pstate & PSR_AA32_V_BIT ? 'V' : 'v',
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pstate & PSR_AA32_Q_BIT ? 'Q' : 'q',
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pstate & PSR_AA32_T_BIT ? "T32" : "A32",
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pstate & PSR_AA32_E_BIT ? "BE" : "LE",
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pstate & PSR_AA32_A_BIT ? 'A' : 'a',
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pstate & PSR_AA32_I_BIT ? 'I' : 'i',
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pstate & PSR_AA32_F_BIT ? 'F' : 'f');
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} else {
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printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO)\n",
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pstate,
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pstate & PSR_N_BIT ? 'N' : 'n',
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pstate & PSR_Z_BIT ? 'Z' : 'z',
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pstate & PSR_C_BIT ? 'C' : 'c',
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pstate & PSR_V_BIT ? 'V' : 'v',
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pstate & PSR_D_BIT ? 'D' : 'd',
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pstate & PSR_A_BIT ? 'A' : 'a',
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pstate & PSR_I_BIT ? 'I' : 'i',
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pstate & PSR_F_BIT ? 'F' : 'f',
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pstate & PSR_PAN_BIT ? '+' : '-',
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pstate & PSR_UAO_BIT ? '+' : '-');
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}
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}
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void __show_regs(struct pt_regs *regs)
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{
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int i, top_reg;
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u64 lr, sp;
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if (compat_user_mode(regs)) {
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lr = regs->compat_lr;
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sp = regs->compat_sp;
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top_reg = 12;
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} else {
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lr = regs->regs[30];
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sp = regs->sp;
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top_reg = 29;
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}
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show_regs_print_info(KERN_DEFAULT);
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print_pstate(regs);
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if (!user_mode(regs)) {
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printk("pc : %pS\n", (void *)regs->pc);
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printk("lr : %pS\n", (void *)lr);
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} else {
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printk("pc : %016llx\n", regs->pc);
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printk("lr : %016llx\n", lr);
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}
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printk("sp : %016llx\n", sp);
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if (system_uses_irq_prio_masking())
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printk("pmr_save: %08llx\n", regs->pmr_save);
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i = top_reg;
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while (i >= 0) {
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printk("x%-2d: %016llx ", i, regs->regs[i]);
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i--;
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if (i % 2 == 0) {
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pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
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i--;
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}
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pr_cont("\n");
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}
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}
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void show_regs(struct pt_regs * regs)
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{
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__show_regs(regs);
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dump_backtrace(regs, NULL);
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}
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static void tls_thread_flush(void)
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{
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write_sysreg(0, tpidr_el0);
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if (is_compat_task()) {
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current->thread.uw.tp_value = 0;
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/*
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* We need to ensure ordering between the shadow state and the
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* hardware state, so that we don't corrupt the hardware state
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* with a stale shadow state during context switch.
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*/
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barrier();
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write_sysreg(0, tpidrro_el0);
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}
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}
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void flush_thread(void)
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{
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fpsimd_flush_thread();
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tls_thread_flush();
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flush_ptrace_hw_breakpoint(current);
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}
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void release_thread(struct task_struct *dead_task)
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{
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}
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void arch_release_task_struct(struct task_struct *tsk)
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{
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fpsimd_release_task(tsk);
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}
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/*
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* src and dst may temporarily have aliased sve_state after task_struct
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* is copied. We cannot fix this properly here, because src may have
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* live SVE state and dst's thread_info may not exist yet, so tweaking
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* either src's or dst's TIF_SVE is not safe.
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*
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* The unaliasing is done in copy_thread() instead. This works because
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* dst is not schedulable or traceable until both of these functions
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* have been called.
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*/
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int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
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{
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if (current->mm)
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fpsimd_preserve_current_state();
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*dst = *src;
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return 0;
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}
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asmlinkage void ret_from_fork(void) asm("ret_from_fork");
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int copy_thread(unsigned long clone_flags, unsigned long stack_start,
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unsigned long stk_sz, struct task_struct *p)
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{
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struct pt_regs *childregs = task_pt_regs(p);
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memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
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/*
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* Unalias p->thread.sve_state (if any) from the parent task
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* and disable discard SVE state for p:
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*/
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clear_tsk_thread_flag(p, TIF_SVE);
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p->thread.sve_state = NULL;
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/*
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* In case p was allocated the same task_struct pointer as some
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* other recently-exited task, make sure p is disassociated from
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* any cpu that may have run that now-exited task recently.
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* Otherwise we could erroneously skip reloading the FPSIMD
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* registers for p.
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*/
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fpsimd_flush_task_state(p);
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if (likely(!(p->flags & PF_KTHREAD))) {
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*childregs = *current_pt_regs();
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childregs->regs[0] = 0;
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/*
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* Read the current TLS pointer from tpidr_el0 as it may be
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* out-of-sync with the saved value.
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*/
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*task_user_tls(p) = read_sysreg(tpidr_el0);
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if (stack_start) {
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if (is_compat_thread(task_thread_info(p)))
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childregs->compat_sp = stack_start;
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else
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childregs->sp = stack_start;
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}
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/*
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* If a TLS pointer was passed to clone (4th argument), use it
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* for the new thread.
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*/
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if (clone_flags & CLONE_SETTLS)
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p->thread.uw.tp_value = childregs->regs[3];
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} else {
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memset(childregs, 0, sizeof(struct pt_regs));
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childregs->pstate = PSR_MODE_EL1h;
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if (IS_ENABLED(CONFIG_ARM64_UAO) &&
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cpus_have_const_cap(ARM64_HAS_UAO))
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childregs->pstate |= PSR_UAO_BIT;
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if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE)
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set_ssbs_bit(childregs);
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if (system_uses_irq_prio_masking())
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childregs->pmr_save = GIC_PRIO_IRQON;
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p->thread.cpu_context.x19 = stack_start;
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p->thread.cpu_context.x20 = stk_sz;
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}
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p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
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p->thread.cpu_context.sp = (unsigned long)childregs;
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ptrace_hw_copy_thread(p);
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return 0;
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}
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void tls_preserve_current_state(void)
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{
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*task_user_tls(current) = read_sysreg(tpidr_el0);
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}
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static void tls_thread_switch(struct task_struct *next)
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{
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tls_preserve_current_state();
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if (is_compat_thread(task_thread_info(next)))
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write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
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else if (!arm64_kernel_unmapped_at_el0())
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write_sysreg(0, tpidrro_el0);
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write_sysreg(*task_user_tls(next), tpidr_el0);
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}
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/* Restore the UAO state depending on next's addr_limit */
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void uao_thread_switch(struct task_struct *next)
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{
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if (IS_ENABLED(CONFIG_ARM64_UAO)) {
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if (task_thread_info(next)->addr_limit == KERNEL_DS)
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asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
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else
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asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
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}
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}
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/*
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* Force SSBS state on context-switch, since it may be lost after migrating
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* from a CPU which treats the bit as RES0 in a heterogeneous system.
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*/
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static void ssbs_thread_switch(struct task_struct *next)
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{
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struct pt_regs *regs = task_pt_regs(next);
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/*
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* Nothing to do for kernel threads, but 'regs' may be junk
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* (e.g. idle task) so check the flags and bail early.
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*/
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if (unlikely(next->flags & PF_KTHREAD))
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return;
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/* If the mitigation is enabled, then we leave SSBS clear. */
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if ((arm64_get_ssbd_state() == ARM64_SSBD_FORCE_ENABLE) ||
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test_tsk_thread_flag(next, TIF_SSBD))
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return;
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if (compat_user_mode(regs))
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set_compat_ssbs_bit(regs);
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else if (user_mode(regs))
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set_ssbs_bit(regs);
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}
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/*
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* We store our current task in sp_el0, which is clobbered by userspace. Keep a
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* shadow copy so that we can restore this upon entry from userspace.
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*
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* This is *only* for exception entry from EL0, and is not valid until we
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* __switch_to() a user task.
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*/
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DEFINE_PER_CPU(struct task_struct *, __entry_task);
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static void entry_task_switch(struct task_struct *next)
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{
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__this_cpu_write(__entry_task, next);
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}
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/*
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* Thread switching.
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*/
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__notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
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struct task_struct *next)
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{
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struct task_struct *last;
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fpsimd_thread_switch(next);
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tls_thread_switch(next);
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hw_breakpoint_thread_switch(next);
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contextidr_thread_switch(next);
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entry_task_switch(next);
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uao_thread_switch(next);
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ptrauth_thread_switch(next);
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ssbs_thread_switch(next);
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/*
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* Complete any pending TLB or cache maintenance on this CPU in case
|
|
* the thread migrates to a different CPU.
|
|
* This full barrier is also required by the membarrier system
|
|
* call.
|
|
*/
|
|
dsb(ish);
|
|
|
|
/* the actual thread switch */
|
|
last = cpu_switch_to(prev, next);
|
|
|
|
return last;
|
|
}
|
|
|
|
unsigned long get_wchan(struct task_struct *p)
|
|
{
|
|
struct stackframe frame;
|
|
unsigned long stack_page, ret = 0;
|
|
int count = 0;
|
|
if (!p || p == current || p->state == TASK_RUNNING)
|
|
return 0;
|
|
|
|
stack_page = (unsigned long)try_get_task_stack(p);
|
|
if (!stack_page)
|
|
return 0;
|
|
|
|
start_backtrace(&frame, thread_saved_fp(p), thread_saved_pc(p));
|
|
|
|
do {
|
|
if (unwind_frame(p, &frame))
|
|
goto out;
|
|
if (!in_sched_functions(frame.pc)) {
|
|
ret = frame.pc;
|
|
goto out;
|
|
}
|
|
} while (count ++ < 16);
|
|
|
|
out:
|
|
put_task_stack(p);
|
|
return ret;
|
|
}
|
|
|
|
unsigned long arch_align_stack(unsigned long sp)
|
|
{
|
|
if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
|
|
sp -= get_random_int() & ~PAGE_MASK;
|
|
return sp & ~0xf;
|
|
}
|
|
|
|
unsigned long arch_randomize_brk(struct mm_struct *mm)
|
|
{
|
|
if (is_compat_task())
|
|
return randomize_page(mm->brk, SZ_32M);
|
|
else
|
|
return randomize_page(mm->brk, SZ_1G);
|
|
}
|
|
|
|
/*
|
|
* Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
|
|
*/
|
|
void arch_setup_new_exec(void)
|
|
{
|
|
current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0;
|
|
|
|
ptrauth_thread_init_user(current);
|
|
}
|