d27ac2e02b
The AXI HDL cores provided for Analog Devices reference designs all share some common base registers (e.g. version register at address 0x00). To reduce duplication for this, a common header is added to define these registers as well as bitfields & macros to work with these registers. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
20 lines
474 B
C
20 lines
474 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Analog Devices AXI common registers & definitions
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*
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* Copyright 2019 Analog Devices Inc.
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*
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* https://wiki.analog.com/resources/fpga/docs/axi_ip
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* https://wiki.analog.com/resources/fpga/docs/hdl/regmap
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*/
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#ifndef ADI_AXI_COMMON_H_
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#define ADI_AXI_COMMON_H_
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#define ADI_AXI_REG_VERSION 0x0000
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#define ADI_AXI_PCORE_VER(major, minor, patch) \
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(((major) << 16) | ((minor) << 8) | (patch))
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#endif /* ADI_AXI_COMMON_H_ */
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