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The Intel Running Average Power Limit (RAPL) technology provides platform software with the ability to monitor, control, and get notifications on power usage. This feature is present in all Sandy Bridge and later Intel processors. Newer models allow more fine grained controls to be applied. In RAPL, power control is divided into domains, which include package, DRAM controller, CPU core (Power Plane 0), graphics uncore (power plane 1), etc. The purpose of this driver is to expose the RAPL settings to userspace. Overall, RAPL fits in the new powercap class driver in that platform level power capping controls are exposed via this generic interface. This driver is based on an earlier patch from Zhang Rui. However, while the previous work was mainly focused on thermal monitoring the focus here is on the usability from user space perspective. References: https://lkml.org/lkml/2011/5/26/93 Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
33 lines
1 KiB
Plaintext
33 lines
1 KiB
Plaintext
#
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# Generic power capping sysfs interface configuration
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#
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menuconfig POWERCAP
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bool "Generic powercap sysfs driver"
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help
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The power capping sysfs interface allows kernel subsystems to expose power
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capping settings to user space in a consistent way. Usually, it consists
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of multiple control types that determine which settings may be exposed and
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power zones representing parts of the system that can be subject to power
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capping.
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If you want this code to be compiled in, say Y here.
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if POWERCAP
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# Client driver configurations go here.
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config INTEL_RAPL
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tristate "Intel RAPL Support"
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depends on X86
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default n
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---help---
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This enables support for the Intel Running Average Power Limit (RAPL)
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technology which allows power limits to be enforced and monitored on
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modern Intel processors (Sandy Bridge and later).
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In RAPL, the platform level settings are divided into domains for
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fine grained control. These domains include processor package, DRAM
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controller, CPU core (Power Plance 0), graphics uncore (Power Plane
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1), etc.
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endif
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