8095295292
The DP83822 can be configured to use the RGMII interface. There are independent fixed 3.5ns clock shift (aka internal delay) for the TX and RX paths. This allow either one to be set if the MII interface is RGMII and the value is set in the firmware node. Signed-off-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
406 lines
10 KiB
C
406 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
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*
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* Copyright (C) 2017 Texas Instruments Inc.
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*/
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#include <linux/ethtool.h>
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#include <linux/etherdevice.h>
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#define DP83822_PHY_ID 0x2000a240
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#define DP83825S_PHY_ID 0x2000a140
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#define DP83825I_PHY_ID 0x2000a150
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#define DP83825CM_PHY_ID 0x2000a160
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#define DP83825CS_PHY_ID 0x2000a170
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#define DP83826C_PHY_ID 0x2000a130
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#define DP83826NC_PHY_ID 0x2000a110
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#define DP83822_DEVADDR 0x1f
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#define MII_DP83822_PHYSCR 0x11
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#define MII_DP83822_MISR1 0x12
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#define MII_DP83822_MISR2 0x13
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#define MII_DP83822_RCSR 0x17
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#define MII_DP83822_RESET_CTRL 0x1f
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#define MII_DP83822_GENCFG 0x465
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#define DP83822_HW_RESET BIT(15)
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#define DP83822_SW_RESET BIT(14)
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/* PHYSCR Register Fields */
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#define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
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#define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */
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/* MISR1 bits */
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#define DP83822_RX_ERR_HF_INT_EN BIT(0)
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#define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
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#define DP83822_ANEG_COMPLETE_INT_EN BIT(2)
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#define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3)
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#define DP83822_SPEED_CHANGED_INT_EN BIT(4)
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#define DP83822_LINK_STAT_INT_EN BIT(5)
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#define DP83822_ENERGY_DET_INT_EN BIT(6)
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#define DP83822_LINK_QUAL_INT_EN BIT(7)
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/* MISR2 bits */
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#define DP83822_JABBER_DET_INT_EN BIT(0)
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#define DP83822_WOL_PKT_INT_EN BIT(1)
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#define DP83822_SLEEP_MODE_INT_EN BIT(2)
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#define DP83822_MDI_XOVER_INT_EN BIT(3)
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#define DP83822_LB_FIFO_INT_EN BIT(4)
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#define DP83822_PAGE_RX_INT_EN BIT(5)
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#define DP83822_ANEG_ERR_INT_EN BIT(6)
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#define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
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/* INT_STAT1 bits */
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#define DP83822_WOL_INT_EN BIT(4)
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#define DP83822_WOL_INT_STAT BIT(12)
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#define MII_DP83822_RXSOP1 0x04a5
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#define MII_DP83822_RXSOP2 0x04a6
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#define MII_DP83822_RXSOP3 0x04a7
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/* WoL Registers */
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#define MII_DP83822_WOL_CFG 0x04a0
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#define MII_DP83822_WOL_STAT 0x04a1
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#define MII_DP83822_WOL_DA1 0x04a2
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#define MII_DP83822_WOL_DA2 0x04a3
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#define MII_DP83822_WOL_DA3 0x04a4
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/* WoL bits */
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#define DP83822_WOL_MAGIC_EN BIT(0)
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#define DP83822_WOL_SECURE_ON BIT(5)
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#define DP83822_WOL_EN BIT(7)
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#define DP83822_WOL_INDICATION_SEL BIT(8)
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#define DP83822_WOL_CLR_INDICATION BIT(11)
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/* RSCR bits */
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#define DP83822_RX_CLK_SHIFT BIT(12)
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#define DP83822_TX_CLK_SHIFT BIT(11)
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static int dp83822_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = phy_read(phydev, MII_DP83822_MISR1);
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if (err < 0)
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return err;
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err = phy_read(phydev, MII_DP83822_MISR2);
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if (err < 0)
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return err;
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return 0;
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}
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static int dp83822_set_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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struct net_device *ndev = phydev->attached_dev;
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u16 value;
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const u8 *mac;
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if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
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mac = (const u8 *)ndev->dev_addr;
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if (!is_valid_ether_addr(mac))
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return -EINVAL;
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/* MAC addresses start with byte 5, but stored in mac[0].
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* 822 PHYs store bytes 4|5, 2|3, 0|1
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*/
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
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(mac[1] << 8) | mac[0]);
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
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(mac[3] << 8) | mac[2]);
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
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(mac[5] << 8) | mac[4]);
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value = phy_read_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_WOL_CFG);
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if (wol->wolopts & WAKE_MAGIC)
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value |= DP83822_WOL_MAGIC_EN;
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else
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value &= ~DP83822_WOL_MAGIC_EN;
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if (wol->wolopts & WAKE_MAGICSECURE) {
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phy_write_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_RXSOP1,
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(wol->sopass[1] << 8) | wol->sopass[0]);
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phy_write_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_RXSOP2,
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(wol->sopass[3] << 8) | wol->sopass[2]);
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phy_write_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_RXSOP3,
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(wol->sopass[5] << 8) | wol->sopass[4]);
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value |= DP83822_WOL_SECURE_ON;
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} else {
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value &= ~DP83822_WOL_SECURE_ON;
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}
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/* Clear any pending WoL interrupt */
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phy_read(phydev, MII_DP83822_MISR2);
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value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
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DP83822_WOL_CLR_INDICATION;
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return phy_write_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_WOL_CFG, value);
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} else {
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return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_WOL_CFG, DP83822_WOL_EN);
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}
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}
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static void dp83822_get_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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int value;
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u16 sopass_val;
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wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
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wol->wolopts = 0;
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value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
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if (value & DP83822_WOL_MAGIC_EN)
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wol->wolopts |= WAKE_MAGIC;
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if (value & DP83822_WOL_SECURE_ON) {
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sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_RXSOP1);
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wol->sopass[0] = (sopass_val & 0xff);
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wol->sopass[1] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_RXSOP2);
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wol->sopass[2] = (sopass_val & 0xff);
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wol->sopass[3] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_RXSOP3);
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wol->sopass[4] = (sopass_val & 0xff);
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wol->sopass[5] = (sopass_val >> 8);
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wol->wolopts |= WAKE_MAGICSECURE;
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}
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/* WoL is not enabled so set wolopts to 0 */
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if (!(value & DP83822_WOL_EN))
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wol->wolopts = 0;
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}
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static int dp83822_config_intr(struct phy_device *phydev)
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{
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int misr_status;
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int physcr_status;
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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misr_status = phy_read(phydev, MII_DP83822_MISR1);
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if (misr_status < 0)
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return misr_status;
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misr_status |= (DP83822_RX_ERR_HF_INT_EN |
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DP83822_FALSE_CARRIER_HF_INT_EN |
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DP83822_ANEG_COMPLETE_INT_EN |
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DP83822_DUP_MODE_CHANGE_INT_EN |
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DP83822_SPEED_CHANGED_INT_EN |
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DP83822_LINK_STAT_INT_EN |
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DP83822_ENERGY_DET_INT_EN |
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DP83822_LINK_QUAL_INT_EN);
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err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
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if (err < 0)
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return err;
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misr_status = phy_read(phydev, MII_DP83822_MISR2);
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if (misr_status < 0)
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return misr_status;
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misr_status |= (DP83822_JABBER_DET_INT_EN |
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DP83822_WOL_PKT_INT_EN |
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DP83822_SLEEP_MODE_INT_EN |
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DP83822_MDI_XOVER_INT_EN |
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DP83822_LB_FIFO_INT_EN |
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DP83822_PAGE_RX_INT_EN |
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DP83822_ANEG_ERR_INT_EN |
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DP83822_EEE_ERROR_CHANGE_INT_EN);
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err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
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if (err < 0)
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return err;
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physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
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if (physcr_status < 0)
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return physcr_status;
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physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
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} else {
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err = phy_write(phydev, MII_DP83822_MISR1, 0);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_DP83822_MISR1, 0);
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if (err < 0)
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return err;
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physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
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if (physcr_status < 0)
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return physcr_status;
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physcr_status &= ~DP83822_PHYSCR_INTEN;
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}
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return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
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}
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static int dp8382x_disable_wol(struct phy_device *phydev)
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{
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int value = DP83822_WOL_EN | DP83822_WOL_MAGIC_EN |
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DP83822_WOL_SECURE_ON;
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return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_WOL_CFG, value);
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}
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static int dp83822_config_init(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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int rgmii_delay;
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s32 rx_int_delay;
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s32 tx_int_delay;
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int err = 0;
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if (phy_interface_is_rgmii(phydev)) {
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rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
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true);
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if (rx_int_delay <= 0)
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rgmii_delay = 0;
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else
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rgmii_delay = DP83822_RX_CLK_SHIFT;
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tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
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false);
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if (tx_int_delay <= 0)
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rgmii_delay &= ~DP83822_TX_CLK_SHIFT;
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else
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rgmii_delay |= DP83822_TX_CLK_SHIFT;
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if (rgmii_delay) {
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err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_RCSR, rgmii_delay);
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if (err)
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return err;
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}
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}
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return dp8382x_disable_wol(phydev);
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}
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static int dp8382x_config_init(struct phy_device *phydev)
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{
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return dp8382x_disable_wol(phydev);
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}
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static int dp83822_phy_reset(struct phy_device *phydev)
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{
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int err;
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err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_HW_RESET);
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if (err < 0)
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return err;
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return phydev->drv->config_init(phydev);
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}
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static int dp83822_suspend(struct phy_device *phydev)
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{
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int value;
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value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
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if (!(value & DP83822_WOL_EN))
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genphy_suspend(phydev);
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return 0;
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}
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static int dp83822_resume(struct phy_device *phydev)
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{
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int value;
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genphy_resume(phydev);
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value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |
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DP83822_WOL_CLR_INDICATION);
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return 0;
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}
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#define DP83822_PHY_DRIVER(_id, _name) \
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{ \
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PHY_ID_MATCH_MODEL(_id), \
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.name = (_name), \
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/* PHY_BASIC_FEATURES */ \
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.soft_reset = dp83822_phy_reset, \
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.config_init = dp83822_config_init, \
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.get_wol = dp83822_get_wol, \
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.set_wol = dp83822_set_wol, \
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.ack_interrupt = dp83822_ack_interrupt, \
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.config_intr = dp83822_config_intr, \
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.suspend = dp83822_suspend, \
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.resume = dp83822_resume, \
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}
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#define DP8382X_PHY_DRIVER(_id, _name) \
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{ \
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PHY_ID_MATCH_MODEL(_id), \
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.name = (_name), \
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/* PHY_BASIC_FEATURES */ \
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.soft_reset = dp83822_phy_reset, \
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.config_init = dp8382x_config_init, \
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.get_wol = dp83822_get_wol, \
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.set_wol = dp83822_set_wol, \
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.ack_interrupt = dp83822_ack_interrupt, \
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.config_intr = dp83822_config_intr, \
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.suspend = dp83822_suspend, \
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.resume = dp83822_resume, \
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}
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static struct phy_driver dp83822_driver[] = {
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DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
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DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
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DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
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DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
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DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
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DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
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DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
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};
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module_phy_driver(dp83822_driver);
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static struct mdio_device_id __maybe_unused dp83822_tbl[] = {
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{ DP83822_PHY_ID, 0xfffffff0 },
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{ DP83825I_PHY_ID, 0xfffffff0 },
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{ DP83826C_PHY_ID, 0xfffffff0 },
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{ DP83826NC_PHY_ID, 0xfffffff0 },
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{ DP83825S_PHY_ID, 0xfffffff0 },
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{ DP83825CM_PHY_ID, 0xfffffff0 },
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{ DP83825CS_PHY_ID, 0xfffffff0 },
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{ },
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};
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MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
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MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
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MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
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MODULE_LICENSE("GPL v2");
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