![Magnus Damm](/assets/img/avatar_default.png)
Enable IRQ_TYPE_EDGE_BOTH on all R/SH-Mobile ARM SoCs. This hardware feature is supported by sh7367, sh7377, sh7372 and sh73a0. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
233 lines
5.9 KiB
C
233 lines
5.9 KiB
C
/*
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* IRQ chip definitions for INTC IRQs.
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*
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* Copyright (C) 2007, 2008 Magnus Damm
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* Copyright (C) 2009, 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/cpumask.h>
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#include <linux/io.h>
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#include "internals.h"
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void _intc_enable(struct irq_data *data, unsigned long handle)
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{
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unsigned int irq = data->irq;
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long addr;
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unsigned int cpu;
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
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#ifdef CONFIG_SMP
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if (!cpumask_test_cpu(cpu, data->affinity))
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continue;
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#endif
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addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
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intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
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[_INTC_FN(handle)], irq);
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}
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intc_balancing_enable(irq);
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}
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static void intc_enable(struct irq_data *data)
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{
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_intc_enable(data, (unsigned long)irq_data_get_irq_chip_data(data));
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}
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static void intc_disable(struct irq_data *data)
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{
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unsigned int irq = data->irq;
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long handle = (unsigned long)irq_data_get_irq_chip_data(data);
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unsigned long addr;
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unsigned int cpu;
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intc_balancing_disable(irq);
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
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#ifdef CONFIG_SMP
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if (!cpumask_test_cpu(cpu, data->affinity))
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continue;
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#endif
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addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
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intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
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[_INTC_FN(handle)], irq);
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}
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}
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static int intc_set_wake(struct irq_data *data, unsigned int on)
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{
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return 0; /* allow wakeup, but setup hardware in intc_suspend() */
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}
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#ifdef CONFIG_SMP
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/*
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* This is held with the irq desc lock held, so we don't require any
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* additional locking here at the intc desc level. The affinity mask is
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* later tested in the enable/disable paths.
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*/
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static int intc_set_affinity(struct irq_data *data,
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const struct cpumask *cpumask,
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bool force)
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{
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if (!cpumask_intersects(cpumask, cpu_online_mask))
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return -1;
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cpumask_copy(data->affinity, cpumask);
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return 0;
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}
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#endif
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static void intc_mask_ack(struct irq_data *data)
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{
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unsigned int irq = data->irq;
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long handle = intc_get_ack_handle(irq);
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unsigned long addr;
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intc_disable(data);
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/* read register and write zero only to the associated bit */
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if (handle) {
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unsigned int value;
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addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
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value = intc_set_field_from_handle(0, 1, handle);
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switch (_INTC_FN(handle)) {
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case REG_FN_MODIFY_BASE + 0: /* 8bit */
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__raw_readb(addr);
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__raw_writeb(0xff ^ value, addr);
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break;
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case REG_FN_MODIFY_BASE + 1: /* 16bit */
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__raw_readw(addr);
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__raw_writew(0xffff ^ value, addr);
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break;
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case REG_FN_MODIFY_BASE + 3: /* 32bit */
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__raw_readl(addr);
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__raw_writel(0xffffffff ^ value, addr);
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break;
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default:
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BUG();
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break;
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}
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}
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}
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static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
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unsigned int nr_hp,
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unsigned int irq)
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{
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int i;
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/*
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* this doesn't scale well, but...
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*
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* this function should only be used for cerain uncommon
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* operations such as intc_set_priority() and intc_set_type()
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* and in those rare cases performance doesn't matter that much.
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* keeping the memory footprint low is more important.
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*
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* one rather simple way to speed this up and still keep the
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* memory footprint down is to make sure the array is sorted
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* and then perform a bisect to lookup the irq.
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*/
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for (i = 0; i < nr_hp; i++) {
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if ((hp + i)->irq != irq)
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continue;
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return hp + i;
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}
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return NULL;
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}
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int intc_set_priority(unsigned int irq, unsigned int prio)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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struct irq_data *data = irq_get_irq_data(irq);
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struct intc_handle_int *ihp;
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if (!intc_get_prio_level(irq) || prio <= 1)
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return -EINVAL;
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ihp = intc_find_irq(d->prio, d->nr_prio, irq);
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if (ihp) {
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if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
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return -EINVAL;
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intc_set_prio_level(irq, prio);
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/*
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* only set secondary masking method directly
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* primary masking method is using intc_prio_level[irq]
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* priority level will be set during next enable()
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*/
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if (_INTC_FN(ihp->handle) != REG_FN_ERR)
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_intc_enable(data, ihp->handle);
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}
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return 0;
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}
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#define SENSE_VALID_FLAG 0x80
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#define VALID(x) (x | SENSE_VALID_FLAG)
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static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
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[IRQ_TYPE_EDGE_FALLING] = VALID(0),
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[IRQ_TYPE_EDGE_RISING] = VALID(1),
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[IRQ_TYPE_LEVEL_LOW] = VALID(2),
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/* SH7706, SH7707 and SH7709 do not support high level triggered */
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#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
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!defined(CONFIG_CPU_SUBTYPE_SH7707) && \
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!defined(CONFIG_CPU_SUBTYPE_SH7709)
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[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
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#endif
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#if defined(CONFIG_ARM) /* all recent SH-Mobile / R-Mobile ARM support this */
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[IRQ_TYPE_EDGE_BOTH] = VALID(4),
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#endif
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};
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static int intc_set_type(struct irq_data *data, unsigned int type)
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{
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unsigned int irq = data->irq;
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
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struct intc_handle_int *ihp;
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unsigned long addr;
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if (!value)
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return -EINVAL;
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value &= ~SENSE_VALID_FLAG;
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ihp = intc_find_irq(d->sense, d->nr_sense, irq);
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if (ihp) {
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/* PINT has 2-bit sense registers, should fail on EDGE_BOTH */
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if (value >= (1 << _INTC_WIDTH(ihp->handle)))
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return -EINVAL;
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addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
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intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
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}
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return 0;
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}
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struct irq_chip intc_irq_chip = {
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.irq_mask = intc_disable,
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.irq_unmask = intc_enable,
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.irq_mask_ack = intc_mask_ack,
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.irq_enable = intc_enable,
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.irq_disable = intc_disable,
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.irq_shutdown = intc_disable,
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.irq_set_type = intc_set_type,
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.irq_set_wake = intc_set_wake,
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#ifdef CONFIG_SMP
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.irq_set_affinity = intc_set_affinity,
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#endif
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};
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