5a148af669
Pull powerpc update from Benjamin Herrenschmidt:
"The main highlights this time around are:
- A pile of addition POWER8 bits and nits, such as updated
performance counter support (Michael Ellerman), new branch history
buffer support (Anshuman Khandual), base support for the new PCI
host bridge when not using the hypervisor (Gavin Shan) and other
random related bits and fixes from various contributors.
- Some rework of our page table format by Aneesh Kumar which fixes a
thing or two and paves the way for THP support. THP itself will
not make it this time around however.
- More Freescale updates, including Altivec support on the new e6500
cores, new PCI controller support, and a pile of new boards support
and updates.
- The usual batch of trivial cleanups & fixes"
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (156 commits)
powerpc: Fix build error for book3e
powerpc: Context switch the new EBB SPRs
powerpc: Turn on the EBB H/FSCR bits
powerpc: Replace CPU_FTR_BCTAR with CPU_FTR_ARCH_207S
powerpc: Setup BHRB instructions facility in HFSCR for POWER8
powerpc: Fix interrupt range check on debug exception
powerpc: Update tlbie/tlbiel as per ISA doc
powerpc: Print page size info during boot
powerpc: print both base and actual page size on hash failure
powerpc: Fix hpte_decode to use the correct decoding for page sizes
powerpc: Decode the pte-lp-encoding bits correctly.
powerpc: Use encode avpn where we need only avpn values
powerpc: Reduce PTE table memory wastage
powerpc: Move the pte free routines from common header
powerpc: Reduce the PTE_INDEX_SIZE
powerpc: Switch 16GB and 16MB explicit hugepages to a different page table format
powerpc: New hugepage directory format
powerpc: Don't truncate pgd_index wrongly
powerpc: Don't hard code the size of pte page
powerpc: Save DAR and DSISR in pt_regs on MCE
...
147 lines
3.2 KiB
Plaintext
147 lines
3.2 KiB
Plaintext
menu "Memory management options"
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config PAGE_OFFSET
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hex "Kernel page offset address"
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default "0x40000000"
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help
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This option allows you to set the virtual address at which the
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kernel will be mapped to.
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endmenu
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config KERNEL_4M_PAGES
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bool "Map kernel with 4MB pages"
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depends on METAG_META21_MMU
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default y
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help
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Map the kernel with large pages to reduce TLB pressure.
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choice
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prompt "User page size"
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default PAGE_SIZE_4K
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config PAGE_SIZE_4K
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bool "4kB"
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help
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This is the default page size used by all Meta cores.
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config PAGE_SIZE_8K
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bool "8kB"
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depends on METAG_META21_MMU
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help
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This enables 8kB pages as supported by Meta 2.x and later MMUs.
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config PAGE_SIZE_16K
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bool "16kB"
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depends on METAG_META21_MMU
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help
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This enables 16kB pages as supported by Meta 2.x and later MMUs.
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endchoice
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config NUMA
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bool "Non Uniform Memory Access (NUMA) Support"
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select ARCH_WANT_NUMA_VARIABLE_LOCALITY
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help
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Some Meta systems have MMU-mappable on-chip memories with
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lower latencies than main memory. This enables support for
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these blocks by binding them to nodes and allowing
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memory policies to be used for prioritizing and controlling
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allocation behaviour.
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config FORCE_MAX_ZONEORDER
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int "Maximum zone order"
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range 10 32
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default "10"
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help
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The kernel memory allocator divides physically contiguous memory
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blocks into "zones", where each zone is a power of two number of
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pages. This option selects the largest power of two that the kernel
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keeps in the memory allocator. If you need to allocate very large
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blocks of physically contiguous memory, then you may need to
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increase this value.
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This config option is actually maximum order plus one. For example,
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a value of 11 means that the largest free memory block is 2^10 pages.
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The page size is not necessarily 4KB. Keep this in mind
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when choosing a value for this option.
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config METAG_L2C
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bool "Level 2 Cache Support"
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depends on METAG_META21
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help
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Press y here to enable support for the Meta Level 2 (L2) cache. This
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will enable the cache at start up if it hasn't already been enabled
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by the bootloader.
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If the bootloader enables the L2 you must press y here to ensure the
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kernel takes the appropriate actions to keep the cache coherent.
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config NODES_SHIFT
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int
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default "1"
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depends on NEED_MULTIPLE_NODES
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config ARCH_FLATMEM_ENABLE
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def_bool y
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depends on !NUMA
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config ARCH_SPARSEMEM_ENABLE
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def_bool y
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select SPARSEMEM_STATIC
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config ARCH_SPARSEMEM_DEFAULT
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def_bool y
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config ARCH_SELECT_MEMORY_MODEL
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def_bool y
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config SYS_SUPPORTS_HUGETLBFS
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def_bool y
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depends on METAG_META21_MMU
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choice
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prompt "HugeTLB page size"
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depends on METAG_META21_MMU && HUGETLB_PAGE
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default HUGETLB_PAGE_SIZE_1M
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config HUGETLB_PAGE_SIZE_8K
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bool "8kB"
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depends on PAGE_SIZE_4K
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config HUGETLB_PAGE_SIZE_16K
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bool "16kB"
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depends on PAGE_SIZE_4K || PAGE_SIZE_8K
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config HUGETLB_PAGE_SIZE_32K
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bool "32kB"
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config HUGETLB_PAGE_SIZE_64K
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bool "64kB"
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config HUGETLB_PAGE_SIZE_128K
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bool "128kB"
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config HUGETLB_PAGE_SIZE_256K
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bool "256kB"
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config HUGETLB_PAGE_SIZE_512K
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bool "512kB"
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config HUGETLB_PAGE_SIZE_1M
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bool "1MB"
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config HUGETLB_PAGE_SIZE_2M
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bool "2MB"
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config HUGETLB_PAGE_SIZE_4M
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bool "4MB"
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endchoice
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config METAG_COREMEM
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bool
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default y if SUSPEND
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source "mm/Kconfig"
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