373cd784d0
Meta has instructions for accessing: - bytes - GETB (1 byte) - words - GETW (2 bytes) - doublewords - GETD (4 bytes) - longwords - GETL (8 bytes) All accesses must be aligned. Unaligned accesses can be detected and made to fault on Meta2, however it isn't possible to fix up unaligned writes so we don't bother fixing up reads either. This patch adds metag memory handling code including: - I/O memory (io.h, ioremap.c): Actually any virtual memory can be accessed with these helpers. A part of the non-MMUable address space is used for memory mapped I/O. The ioremap() function is implemented one to one for non-MMUable addresses. - User memory (uaccess.h, usercopy.c): User memory is directly accessible from privileged code. - Kernel memory (maccess.c): probe_kernel_write() needs to be overwridden to use the I/O functions when doing a simple aligned write to non-writecombined memory, otherwise the write may be split by the generic version. Note that due to the fact that a portion of the virtual address space is non-MMUable, and therefore always maps directly to the physical address space, metag specific I/O functions are made available (metag_in32, metag_out32 etc). These cast the address argument to a pointer so that they can be used with raw physical addresses. These accessors are only to be used for accessing fixed core Meta architecture registers in the non-MMU region, and not for any SoC/peripheral registers. Signed-off-by: James Hogan <james.hogan@imgtec.com>
69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/*
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* safe read and write memory routines callable while atomic
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*
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* Copyright 2012 Imagination Technologies
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*/
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#include <linux/uaccess.h>
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#include <asm/io.h>
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/*
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* The generic probe_kernel_write() uses the user copy code which can split the
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* writes if the source is unaligned, and repeats writes to make exceptions
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* precise. We override it here to avoid these things happening to memory mapped
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* IO memory where they could have undesired effects.
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* Due to the use of CACHERD instruction this only works on Meta2 onwards.
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*/
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#ifdef CONFIG_METAG_META21
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long probe_kernel_write(void *dst, const void *src, size_t size)
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{
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unsigned long ldst = (unsigned long)dst;
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void __iomem *iodst = (void __iomem *)dst;
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unsigned long lsrc = (unsigned long)src;
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const u8 *psrc = (u8 *)src;
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unsigned int pte, i;
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u8 bounce[8] __aligned(8);
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if (!size)
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return 0;
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/* Use the write combine bit to decide is the destination is MMIO. */
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pte = __builtin_meta2_cacherd(dst);
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/* Check the mapping is valid and writeable. */
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if ((pte & (MMCU_ENTRY_WR_BIT | MMCU_ENTRY_VAL_BIT))
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!= (MMCU_ENTRY_WR_BIT | MMCU_ENTRY_VAL_BIT))
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return -EFAULT;
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/* Fall back to generic version for cases we're not interested in. */
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if (pte & MMCU_ENTRY_WRC_BIT || /* write combined memory */
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(ldst & (size - 1)) || /* destination unaligned */
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size > 8 || /* more than max write size */
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(size & (size - 1))) /* non power of 2 size */
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return __probe_kernel_write(dst, src, size);
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/* If src is unaligned, copy to the aligned bounce buffer first. */
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if (lsrc & (size - 1)) {
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for (i = 0; i < size; ++i)
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bounce[i] = psrc[i];
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psrc = bounce;
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}
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switch (size) {
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case 1:
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writeb(*psrc, iodst);
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break;
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case 2:
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writew(*(const u16 *)psrc, iodst);
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break;
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case 4:
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writel(*(const u32 *)psrc, iodst);
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break;
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case 8:
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writeq(*(const u64 *)psrc, iodst);
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break;
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}
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return 0;
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}
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#endif
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