37b3a8ff3e
The impetus for this is that we would like to move to 64-bit PMDs and PGDs, but that would result in only supporting a 42-bit address space with the current page table layout. It'd be nice to support at least 43-bits. The reason we'd end up with only 42-bits after making PMDs and PGDs 64-bit is that we only use half-page sized PTE tables in order to make PMDs line up to 4MB, the hardware huge page size we use. So what we do here is we make huge pages 8MB, and fabricate them using 4MB hw TLB entries. Facilitate this by providing a "REAL_HPAGE_SHIFT" which is used in places that really need to operate on hardware 4MB pages. Use full pages (512 entries) for PTE tables, and adjust PMD_SHIFT, PGD_SHIFT, and the build time CPP test as needed. Use a CPP test to make sure REAL_HPAGE_SHIFT and the _PAGE_SZHUGE_* we use match up. This makes the pgtable cache completely unused, so remove the code managing it and the state used in mm_context_t. Now we have less spinlocks taken in the page table allocation path. The technique we use to fabricate the 8MB pages is to transfer bit 22 from the missing virtual address into the PTEs physical address field. That takes care of the transparent huge pages case. For hugetlb, we fill things in at the PTE level and that code already puts the sub huge page physical bits into the PTEs, based upon the offset, so there is nothing special we need to do. It all just works out. So, a small amount of complexity in the THP case, but this code is about to get much simpler when we move the 64-bit PMDs as we can move away from the fancy 32-bit huge PMD encoding and just put a real PTE value in there. With bug fixes and help from Bob Picco. Signed-off-by: David S. Miller <davem@davemloft.net>
583 lines
13 KiB
ArmAsm
583 lines
13 KiB
ArmAsm
/* tsb.S: Sparc64 TSB table handling.
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*
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* Copyright (C) 2006 David S. Miller <davem@davemloft.net>
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*/
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#include <asm/tsb.h>
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#include <asm/hypervisor.h>
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#include <asm/page.h>
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#include <asm/cpudata.h>
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#include <asm/mmu.h>
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.text
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.align 32
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/* Invoked from TLB miss handler, we are in the
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* MMU global registers and they are setup like
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* this:
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*
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* %g1: TSB entry pointer
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* %g2: available temporary
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* %g3: FAULT_CODE_{D,I}TLB
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* %g4: available temporary
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* %g5: available temporary
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* %g6: TAG TARGET
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* %g7: available temporary, will be loaded by us with
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* the physical address base of the linux page
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* tables for the current address space
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*/
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tsb_miss_dtlb:
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mov TLB_TAG_ACCESS, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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ldxa [%g4] ASI_DMMU, %g4
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tsb_miss_itlb:
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mov TLB_TAG_ACCESS, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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ldxa [%g4] ASI_IMMU, %g4
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/* At this point we have:
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* %g1 -- PAGE_SIZE TSB entry address
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* %g3 -- FAULT_CODE_{D,I}TLB
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* %g4 -- missing virtual address
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* %g6 -- TAG TARGET (vaddr >> 22)
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*/
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tsb_miss_page_table_walk:
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TRAP_LOAD_TRAP_BLOCK(%g7, %g5)
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/* Before committing to a full page table walk,
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* check the huge page TSB.
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*/
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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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661: ldx [%g7 + TRAP_PER_CPU_TSB_HUGE], %g5
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nop
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov SCRATCHPAD_UTSBREG2, %g5
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ldxa [%g5] ASI_SCRATCHPAD, %g5
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.previous
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cmp %g5, -1
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be,pt %xcc, 80f
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nop
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/* We need an aligned pair of registers containing 2 values
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* which can be easily rematerialized. %g6 and %g7 foot the
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* bill just nicely. We'll save %g6 away into %g2 for the
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* huge page TSB TAG comparison.
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*
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* Perform a huge page TSB lookup.
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*/
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mov %g6, %g2
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and %g5, 0x7, %g6
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mov 512, %g7
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andn %g5, 0x7, %g5
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sllx %g7, %g6, %g7
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srlx %g4, REAL_HPAGE_SHIFT, %g6
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sub %g7, 1, %g7
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and %g6, %g7, %g6
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sllx %g6, 4, %g6
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add %g5, %g6, %g5
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TSB_LOAD_QUAD(%g5, %g6)
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cmp %g6, %g2
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be,a,pt %xcc, tsb_tlb_reload
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mov %g7, %g5
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/* No match, remember the huge page TSB entry address,
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* and restore %g6 and %g7.
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*/
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TRAP_LOAD_TRAP_BLOCK(%g7, %g6)
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srlx %g4, 22, %g6
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80: stx %g5, [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP]
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#endif
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ldx [%g7 + TRAP_PER_CPU_PGD_PADDR], %g7
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/* At this point we have:
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* %g1 -- TSB entry address
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* %g3 -- FAULT_CODE_{D,I}TLB
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* %g4 -- missing virtual address
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* %g6 -- TAG TARGET (vaddr >> 22)
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* %g7 -- page table physical address
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*
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* We know that both the base PAGE_SIZE TSB and the HPAGE_SIZE
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* TSB both lack a matching entry.
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*/
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tsb_miss_page_table_walk_sun4v_fastpath:
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USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
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/* Valid PTE is now in %g5. */
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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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661: sethi %uhi(_PAGE_SZALL_4U), %g7
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sllx %g7, 32, %g7
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov _PAGE_SZALL_4V, %g7
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nop
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.previous
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and %g5, %g7, %g2
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661: sethi %uhi(_PAGE_SZHUGE_4U), %g7
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sllx %g7, 32, %g7
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov _PAGE_SZHUGE_4V, %g7
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nop
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.previous
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cmp %g2, %g7
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bne,pt %xcc, 60f
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nop
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/* It is a huge page, use huge page TSB entry address we
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* calculated above. If the huge page TSB has not been
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* allocated, setup a trap stack and call hugetlb_setup()
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* to do so, then return from the trap to replay the TLB
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* miss.
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*
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* This is necessary to handle the case of transparent huge
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* pages where we don't really have a non-atomic context
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* in which to allocate the hugepage TSB hash table. When
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* the 'mm' faults in the hugepage for the first time, we
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* thus handle it here. This also makes sure that we can
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* allocate the TSB hash table on the correct NUMA node.
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*/
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TRAP_LOAD_TRAP_BLOCK(%g7, %g2)
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ldx [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP], %g1
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cmp %g1, -1
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bne,pt %xcc, 60f
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nop
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661: rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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SET_GL(1)
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nop
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.previous
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rdpr %tl, %g3
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cmp %g3, 1
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bne,pn %xcc, winfix_trampoline
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nop
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ba,pt %xcc, etrap
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rd %pc, %g7
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call hugetlb_setup
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap
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nop
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60:
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#endif
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/* At this point we have:
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* %g1 -- TSB entry address
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* %g3 -- FAULT_CODE_{D,I}TLB
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* %g5 -- valid PTE
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* %g6 -- TAG TARGET (vaddr >> 22)
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*/
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tsb_reload:
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TSB_LOCK_TAG(%g1, %g2, %g7)
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TSB_WRITE(%g1, %g5, %g6)
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/* Finally, load TLB and return from trap. */
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tsb_tlb_reload:
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cmp %g3, FAULT_CODE_DTLB
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bne,pn %xcc, tsb_itlb_load
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nop
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tsb_dtlb_load:
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661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
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retry
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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/* For sun4v the ASI_DTLB_DATA_IN store and the retry
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* instruction get nop'd out and we get here to branch
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* to the sun4v tlb load code. The registers are setup
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* as follows:
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*
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* %g4: vaddr
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* %g5: PTE
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* %g6: TAG
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*
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* The sun4v TLB load wants the PTE in %g3 so we fix that
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* up here.
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*/
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ba,pt %xcc, sun4v_dtlb_load
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mov %g5, %g3
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tsb_itlb_load:
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/* Executable bit must be set. */
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661: sethi %hi(_PAGE_EXEC_4U), %g4
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andcc %g5, %g4, %g0
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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andcc %g5, _PAGE_EXEC_4V, %g0
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nop
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.previous
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be,pn %xcc, tsb_do_fault
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nop
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661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
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retry
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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/* For sun4v the ASI_ITLB_DATA_IN store and the retry
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* instruction get nop'd out and we get here to branch
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* to the sun4v tlb load code. The registers are setup
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* as follows:
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*
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* %g4: vaddr
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* %g5: PTE
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* %g6: TAG
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*
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* The sun4v TLB load wants the PTE in %g3 so we fix that
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* up here.
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*/
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ba,pt %xcc, sun4v_itlb_load
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mov %g5, %g3
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/* No valid entry in the page tables, do full fault
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* processing.
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*/
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.globl tsb_do_fault
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tsb_do_fault:
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cmp %g3, FAULT_CODE_DTLB
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661: rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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SET_GL(1)
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ldxa [%g0] ASI_SCRATCHPAD, %g4
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.previous
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bne,pn %xcc, tsb_do_itlb_fault
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nop
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tsb_do_dtlb_fault:
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rdpr %tl, %g3
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cmp %g3, 1
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661: mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g5
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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ldx [%g4 + HV_FAULT_D_ADDR_OFFSET], %g5
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nop
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.previous
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be,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_DTLB, %g4
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ba,pt %xcc, winfix_trampoline
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nop
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tsb_do_itlb_fault:
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rdpr %tpc, %g5
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ba,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_ITLB, %g4
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.globl sparc64_realfault_common
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sparc64_realfault_common:
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/* fault code in %g4, fault address in %g5, etrap will
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* preserve these two values in %l4 and %l5 respectively
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*/
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ba,pt %xcc, etrap ! Save trap state
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1: rd %pc, %g7 ! ...
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stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
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stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
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call do_sparc64_fault ! Call fault handler
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add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
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ba,pt %xcc, rtrap ! Restore cpu state
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nop ! Delay slot (fill me)
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winfix_trampoline:
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rdpr %tpc, %g3 ! Prepare winfixup TNPC
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or %g3, 0x7c, %g3 ! Compute branch offset
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wrpr %g3, %tnpc ! Write it into TNPC
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done ! Trap return
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/* Insert an entry into the TSB.
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*
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* %o0: TSB entry pointer (virt or phys address)
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* %o1: tag
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* %o2: pte
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*/
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.align 32
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.globl __tsb_insert
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__tsb_insert:
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rdpr %pstate, %o5
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wrpr %o5, PSTATE_IE, %pstate
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TSB_LOCK_TAG(%o0, %g2, %g3)
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TSB_WRITE(%o0, %o2, %o1)
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wrpr %o5, %pstate
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retl
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nop
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.size __tsb_insert, .-__tsb_insert
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/* Flush the given TSB entry if it has the matching
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* tag.
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*
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* %o0: TSB entry pointer (virt or phys address)
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* %o1: tag
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*/
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.align 32
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.globl tsb_flush
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.type tsb_flush,#function
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tsb_flush:
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sethi %hi(TSB_TAG_LOCK_HIGH), %g2
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1: TSB_LOAD_TAG(%o0, %g1)
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srlx %g1, 32, %o3
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andcc %o3, %g2, %g0
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bne,pn %icc, 1b
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nop
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cmp %g1, %o1
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mov 1, %o3
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bne,pt %xcc, 2f
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sllx %o3, TSB_TAG_INVALID_BIT, %o3
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TSB_CAS_TAG(%o0, %g1, %o3)
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cmp %g1, %o3
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bne,pn %xcc, 1b
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nop
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2: retl
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nop
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.size tsb_flush, .-tsb_flush
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/* Reload MMU related context switch state at
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* schedule() time.
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*
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* %o0: page table physical address
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* %o1: TSB base config pointer
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* %o2: TSB huge config pointer, or NULL if none
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* %o3: Hypervisor TSB descriptor physical address
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*
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* We have to run this whole thing with interrupts
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* disabled so that the current cpu doesn't change
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* due to preemption.
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*/
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.align 32
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.globl __tsb_context_switch
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.type __tsb_context_switch,#function
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__tsb_context_switch:
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rdpr %pstate, %g1
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wrpr %g1, PSTATE_IE, %pstate
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TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
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stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
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ldx [%o1 + TSB_CONFIG_REG_VAL], %o0
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brz,pt %o2, 1f
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mov -1, %g3
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ldx [%o2 + TSB_CONFIG_REG_VAL], %g3
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1: stx %g3, [%g2 + TRAP_PER_CPU_TSB_HUGE]
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sethi %hi(tlb_type), %g2
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lduw [%g2 + %lo(tlb_type)], %g2
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cmp %g2, 3
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bne,pt %icc, 50f
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nop
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/* Hypervisor TSB switch. */
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mov SCRATCHPAD_UTSBREG1, %o5
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stxa %o0, [%o5] ASI_SCRATCHPAD
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mov SCRATCHPAD_UTSBREG2, %o5
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stxa %g3, [%o5] ASI_SCRATCHPAD
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mov 2, %o0
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cmp %g3, -1
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move %xcc, 1, %o0
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mov HV_FAST_MMU_TSB_CTXNON0, %o5
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mov %o3, %o1
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ta HV_FAST_TRAP
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/* Finish up. */
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ba,pt %xcc, 9f
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nop
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/* SUN4U TSB switch. */
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50: mov TSB_REG, %o5
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stxa %o0, [%o5] ASI_DMMU
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membar #Sync
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stxa %o0, [%o5] ASI_IMMU
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membar #Sync
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2: ldx [%o1 + TSB_CONFIG_MAP_VADDR], %o4
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brz %o4, 9f
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ldx [%o1 + TSB_CONFIG_MAP_PTE], %o5
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sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2
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mov TLB_TAG_ACCESS, %g3
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lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
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stxa %o4, [%g3] ASI_DMMU
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membar #Sync
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sllx %g2, 3, %g2
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stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
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membar #Sync
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brz,pt %o2, 9f
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nop
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ldx [%o2 + TSB_CONFIG_MAP_VADDR], %o4
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ldx [%o2 + TSB_CONFIG_MAP_PTE], %o5
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mov TLB_TAG_ACCESS, %g3
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stxa %o4, [%g3] ASI_DMMU
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membar #Sync
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sub %g2, (1 << 3), %g2
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stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
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membar #Sync
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9:
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wrpr %g1, %pstate
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retl
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nop
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.size __tsb_context_switch, .-__tsb_context_switch
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#define TSB_PASS_BITS ((1 << TSB_TAG_LOCK_BIT) | \
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(1 << TSB_TAG_INVALID_BIT))
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.align 32
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.globl copy_tsb
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.type copy_tsb,#function
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copy_tsb: /* %o0=old_tsb_base, %o1=old_tsb_size
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* %o2=new_tsb_base, %o3=new_tsb_size
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*/
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sethi %uhi(TSB_PASS_BITS), %g7
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srlx %o3, 4, %o3
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add %o0, %o1, %g1 /* end of old tsb */
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sllx %g7, 32, %g7
|
|
sub %o3, 1, %o3 /* %o3 == new tsb hash mask */
|
|
|
|
661: prefetcha [%o0] ASI_N, #one_read
|
|
.section .tsb_phys_patch, "ax"
|
|
.word 661b
|
|
prefetcha [%o0] ASI_PHYS_USE_EC, #one_read
|
|
.previous
|
|
|
|
90: andcc %o0, (64 - 1), %g0
|
|
bne 1f
|
|
add %o0, 64, %o5
|
|
|
|
661: prefetcha [%o5] ASI_N, #one_read
|
|
.section .tsb_phys_patch, "ax"
|
|
.word 661b
|
|
prefetcha [%o5] ASI_PHYS_USE_EC, #one_read
|
|
.previous
|
|
|
|
1: TSB_LOAD_QUAD(%o0, %g2) /* %g2/%g3 == TSB entry */
|
|
andcc %g2, %g7, %g0 /* LOCK or INVALID set? */
|
|
bne,pn %xcc, 80f /* Skip it */
|
|
sllx %g2, 22, %o4 /* TAG --> VADDR */
|
|
|
|
/* This can definitely be computed faster... */
|
|
srlx %o0, 4, %o5 /* Build index */
|
|
and %o5, 511, %o5 /* Mask index */
|
|
sllx %o5, PAGE_SHIFT, %o5 /* Put into vaddr position */
|
|
or %o4, %o5, %o4 /* Full VADDR. */
|
|
srlx %o4, PAGE_SHIFT, %o4 /* Shift down to create index */
|
|
and %o4, %o3, %o4 /* Mask with new_tsb_nents-1 */
|
|
sllx %o4, 4, %o4 /* Shift back up into tsb ent offset */
|
|
TSB_STORE(%o2 + %o4, %g2) /* Store TAG */
|
|
add %o4, 0x8, %o4 /* Advance to TTE */
|
|
TSB_STORE(%o2 + %o4, %g3) /* Store TTE */
|
|
|
|
80: add %o0, 16, %o0
|
|
cmp %o0, %g1
|
|
bne,pt %xcc, 90b
|
|
nop
|
|
|
|
retl
|
|
nop
|
|
.size copy_tsb, .-copy_tsb
|
|
|
|
/* Set the invalid bit in all TSB entries. */
|
|
.align 32
|
|
.globl tsb_init
|
|
.type tsb_init,#function
|
|
tsb_init: /* %o0 = TSB vaddr, %o1 = size in bytes */
|
|
prefetch [%o0 + 0x000], #n_writes
|
|
mov 1, %g1
|
|
prefetch [%o0 + 0x040], #n_writes
|
|
sllx %g1, TSB_TAG_INVALID_BIT, %g1
|
|
prefetch [%o0 + 0x080], #n_writes
|
|
1: prefetch [%o0 + 0x0c0], #n_writes
|
|
stx %g1, [%o0 + 0x00]
|
|
stx %g1, [%o0 + 0x10]
|
|
stx %g1, [%o0 + 0x20]
|
|
stx %g1, [%o0 + 0x30]
|
|
prefetch [%o0 + 0x100], #n_writes
|
|
stx %g1, [%o0 + 0x40]
|
|
stx %g1, [%o0 + 0x50]
|
|
stx %g1, [%o0 + 0x60]
|
|
stx %g1, [%o0 + 0x70]
|
|
prefetch [%o0 + 0x140], #n_writes
|
|
stx %g1, [%o0 + 0x80]
|
|
stx %g1, [%o0 + 0x90]
|
|
stx %g1, [%o0 + 0xa0]
|
|
stx %g1, [%o0 + 0xb0]
|
|
prefetch [%o0 + 0x180], #n_writes
|
|
stx %g1, [%o0 + 0xc0]
|
|
stx %g1, [%o0 + 0xd0]
|
|
stx %g1, [%o0 + 0xe0]
|
|
stx %g1, [%o0 + 0xf0]
|
|
subcc %o1, 0x100, %o1
|
|
bne,pt %xcc, 1b
|
|
add %o0, 0x100, %o0
|
|
retl
|
|
nop
|
|
nop
|
|
nop
|
|
.size tsb_init, .-tsb_init
|
|
|
|
.globl NGtsb_init
|
|
.type NGtsb_init,#function
|
|
NGtsb_init:
|
|
rd %asi, %g2
|
|
mov 1, %g1
|
|
wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi
|
|
sllx %g1, TSB_TAG_INVALID_BIT, %g1
|
|
1: stxa %g1, [%o0 + 0x00] %asi
|
|
stxa %g1, [%o0 + 0x10] %asi
|
|
stxa %g1, [%o0 + 0x20] %asi
|
|
stxa %g1, [%o0 + 0x30] %asi
|
|
stxa %g1, [%o0 + 0x40] %asi
|
|
stxa %g1, [%o0 + 0x50] %asi
|
|
stxa %g1, [%o0 + 0x60] %asi
|
|
stxa %g1, [%o0 + 0x70] %asi
|
|
stxa %g1, [%o0 + 0x80] %asi
|
|
stxa %g1, [%o0 + 0x90] %asi
|
|
stxa %g1, [%o0 + 0xa0] %asi
|
|
stxa %g1, [%o0 + 0xb0] %asi
|
|
stxa %g1, [%o0 + 0xc0] %asi
|
|
stxa %g1, [%o0 + 0xd0] %asi
|
|
stxa %g1, [%o0 + 0xe0] %asi
|
|
stxa %g1, [%o0 + 0xf0] %asi
|
|
subcc %o1, 0x100, %o1
|
|
bne,pt %xcc, 1b
|
|
add %o0, 0x100, %o0
|
|
membar #Sync
|
|
retl
|
|
wr %g2, 0x0, %asi
|
|
.size NGtsb_init, .-NGtsb_init
|