![Olof Johansson](/assets/img/avatar_default.png)
Erratum 5945 causes some of the registers on the PCIe root ports to not read correctly. Do a small dance to avoid this: Write an unused register, read the value and write it back. Thankfully this is not in a hot code path. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
245 lines
5.6 KiB
C
245 lines
5.6 KiB
C
/*
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* Copyright (C) 2006 PA Semi, Inc
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*
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* Authors: Kip Walker, PA Semi
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* Olof Johansson, PA Semi
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*
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* Maintained by: Olof Johansson <olof@lixom.net>
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*
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* Based on arch/powerpc/platforms/maple/pci.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/ppc-pci.h>
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#define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
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static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset)
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{
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/* Device 0 Function 0 is special: It's config space spans function 1 as
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* well, so allow larger offset. It's really a two-function device but the
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* second function does not probe.
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*/
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if (bus == 0 && devfn == 0)
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return offset < 8192;
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else
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return offset < 4096;
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}
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static void volatile __iomem *pa_pxp_cfg_addr(struct pci_controller *hose,
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u8 bus, u8 devfn, int offset)
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{
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return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset);
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}
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static inline int is_root_port(int busno, int devfn)
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{
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return ((busno == 0) && (PCI_FUNC(devfn) < 4) &&
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((PCI_SLOT(devfn) == 16) || (PCI_SLOT(devfn) == 17)));
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}
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static inline int is_5945_reg(int reg)
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{
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return (((reg >= 0x18) && (reg < 0x34)) ||
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((reg >= 0x158) && (reg < 0x178)));
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}
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static int workaround_5945(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose;
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void volatile __iomem *addr, *dummy;
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int byte;
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u32 tmp;
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if (!is_root_port(bus->number, devfn) || !is_5945_reg(offset))
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return 0;
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hose = pci_bus_to_host(bus);
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addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset & ~0x3);
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byte = offset & 0x3;
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/* Workaround bug 5945: write 0 to a dummy register before reading,
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* and write back what we read. We must read/write the full 32-bit
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* contents so we need to shift and mask by hand.
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*/
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dummy = pa_pxp_cfg_addr(hose, bus->number, devfn, 0x10);
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out_le32(dummy, 0);
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tmp = in_le32(addr);
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out_le32(addr, tmp);
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switch (len) {
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case 1:
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*val = (tmp >> (8*byte)) & 0xff;
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break;
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case 2:
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if (byte == 0)
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*val = tmp & 0xffff;
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else
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*val = (tmp >> 16) & 0xffff;
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break;
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default:
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*val = tmp;
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break;
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}
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return 1;
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}
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static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose;
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void volatile __iomem *addr;
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hose = pci_bus_to_host(bus);
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if (!hose)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (!pa_pxp_offset_valid(bus->number, devfn, offset))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (workaround_5945(bus, devfn, offset, len, val))
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return PCIBIOS_SUCCESSFUL;
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addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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*val = in_8(addr);
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break;
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case 2:
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*val = in_le16(addr);
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break;
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default:
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*val = in_le32(addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose;
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void volatile __iomem *addr;
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hose = pci_bus_to_host(bus);
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if (!hose)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (!pa_pxp_offset_valid(bus->number, devfn, offset))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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out_8(addr, val);
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break;
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case 2:
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out_le16(addr, val);
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break;
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default:
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out_le32(addr, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pa_pxp_ops = {
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.read = pa_pxp_read_config,
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.write = pa_pxp_write_config,
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};
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static void __init setup_pa_pxp(struct pci_controller *hose)
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{
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hose->ops = &pa_pxp_ops;
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hose->cfg_data = ioremap(0xe0000000, 0x10000000);
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}
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static int __init pas_add_bridge(struct device_node *dev)
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{
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struct pci_controller *hose;
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pr_debug("Adding PCI host bridge %s\n", dev->full_name);
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hose = pcibios_alloc_controller(dev);
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if (!hose)
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return -ENOMEM;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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setup_pa_pxp(hose);
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printk(KERN_INFO "Found PA-PXP PCI host bridge.\n");
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/* Interpret the "ranges" property */
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pci_process_bridge_OF_ranges(hose, dev, 1);
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return 0;
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}
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void __init pas_pci_init(void)
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{
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struct device_node *np, *root;
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root = of_find_node_by_path("/");
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if (!root) {
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printk(KERN_CRIT "pas_pci_init: can't find root "
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"of device tree\n");
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return;
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}
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for (np = NULL; (np = of_get_next_child(root, np)) != NULL;)
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if (np->name && !strcmp(np->name, "pxp") && !pas_add_bridge(np))
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of_node_get(np);
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of_node_put(root);
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/* Setup the linkage between OF nodes and PHBs */
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pci_devs_phb_init();
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/* Use the common resource allocation mechanism */
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pci_probe_only = 1;
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}
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void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset)
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{
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struct pci_controller *hose;
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hose = pci_bus_to_host(dev->bus);
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return (void __iomem *)pa_pxp_cfg_addr(hose, dev->bus->number, dev->devfn, offset);
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}
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