32 lines
999 B
Plaintext
32 lines
999 B
Plaintext
Socionext UniPhier PCIe PHY bindings
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This describes the devicetree bindings for PHY interface built into
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PCIe controller implemented on Socionext UniPhier SoCs.
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Required properties:
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- compatible: Should contain one of the following:
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"socionext,uniphier-ld20-pcie-phy" - for LD20 PHY
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"socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY
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- reg: Specifies offset and length of the register set for the device.
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- #phy-cells: Must be zero.
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- clocks: A phandle to the clock gate for PCIe glue layer including
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this phy.
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- resets: A phandle to the reset line for PCIe glue layer including
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this phy.
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Optional properties:
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- socionext,syscon: A phandle to system control to set configurations
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for phy.
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Refer to phy/phy-bindings.txt for the generic PHY binding properties.
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Example:
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pcie_phy: phy@66038000 {
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compatible = "socionext,uniphier-ld20-pcie-phy";
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reg = <0x66038000 0x4000>;
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#phy-cells = <0>;
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clocks = <&sys_clk 24>;
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resets = <&sys_rst 24>;
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socionext,syscon = <&soc_glue>;
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};
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