![Ben Dooks](/assets/img/avatar_default.png)
Patch from Ben Dooks S3C2440 UPLL is the same as the S3C2410 UPLL, it is only the MPLL which has an extra multiplication factor of 2 in the multiplier. Signed-off-by: Ben Dooks Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
508 lines
10 KiB
C
508 lines
10 KiB
C
/* linux/arch/arm/mach-s3c2410/clock.c
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 Clock control support
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*
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* Based on, and code from linux/arch/arm/mach-versatile/clock.c
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**
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** Copyright (C) 2004 ARM Limited.
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** Written by Deep Blue Solutions Limited.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <asm/hardware.h>
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#include <asm/atomic.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/hardware/clock.h>
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#include <asm/arch/regs-clock.h>
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#include "clock.h"
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#include "cpu.h"
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/* clock information */
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static LIST_HEAD(clocks);
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static DECLARE_MUTEX(clocks_sem);
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/* old functions */
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void inline s3c24xx_clk_enable(unsigned int clocks, unsigned int enable)
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{
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unsigned long clkcon;
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unsigned long flags;
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local_irq_save(flags);
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clkcon = __raw_readl(S3C2410_CLKCON);
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clkcon &= ~clocks;
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if (enable)
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clkcon |= clocks;
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/* ensure none of the special function bits set */
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clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
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__raw_writel(clkcon, S3C2410_CLKCON);
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local_irq_restore(flags);
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}
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/* enable and disable calls for use with the clk struct */
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static int clk_null_enable(struct clk *clk, int enable)
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{
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return 0;
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}
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int s3c24xx_clkcon_enable(struct clk *clk, int enable)
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{
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s3c24xx_clk_enable(clk->ctrlbit, enable);
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return 0;
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}
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/* Clock API calls */
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struct clk *clk_get(struct device *dev, const char *id)
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{
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struct clk *p;
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struct clk *clk = ERR_PTR(-ENOENT);
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int idno;
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idno = (dev == NULL) ? -1 : to_platform_device(dev)->id;
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down(&clocks_sem);
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list_for_each_entry(p, &clocks, list) {
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if (p->id == idno &&
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strcmp(id, p->name) == 0 &&
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try_module_get(p->owner)) {
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clk = p;
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break;
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}
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}
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/* check for the case where a device was supplied, but the
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* clock that was being searched for is not device specific */
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if (IS_ERR(clk)) {
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list_for_each_entry(p, &clocks, list) {
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if (p->id == -1 && strcmp(id, p->name) == 0 &&
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try_module_get(p->owner)) {
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clk = p;
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break;
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}
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}
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}
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up(&clocks_sem);
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return clk;
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}
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void clk_put(struct clk *clk)
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{
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module_put(clk->owner);
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}
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int clk_enable(struct clk *clk)
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{
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if (IS_ERR(clk))
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return -EINVAL;
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return (clk->enable)(clk, 1);
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}
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void clk_disable(struct clk *clk)
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{
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if (!IS_ERR(clk))
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(clk->enable)(clk, 0);
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}
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int clk_use(struct clk *clk)
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{
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atomic_inc(&clk->used);
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return 0;
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}
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void clk_unuse(struct clk *clk)
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{
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atomic_dec(&clk->used);
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}
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (IS_ERR(clk))
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return 0;
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if (clk->rate != 0)
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return clk->rate;
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while (clk->parent != NULL && clk->rate == 0)
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clk = clk->parent;
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return clk->rate;
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}
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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return rate;
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}
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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return -EINVAL;
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}
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struct clk *clk_get_parent(struct clk *clk)
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{
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return clk->parent;
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}
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EXPORT_SYMBOL(clk_get);
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EXPORT_SYMBOL(clk_put);
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EXPORT_SYMBOL(clk_enable);
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EXPORT_SYMBOL(clk_disable);
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EXPORT_SYMBOL(clk_use);
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EXPORT_SYMBOL(clk_unuse);
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EXPORT_SYMBOL(clk_get_rate);
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EXPORT_SYMBOL(clk_round_rate);
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EXPORT_SYMBOL(clk_set_rate);
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EXPORT_SYMBOL(clk_get_parent);
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/* base clocks */
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static struct clk clk_xtal = {
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.name = "xtal",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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};
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static struct clk clk_f = {
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.name = "fclk",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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};
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static struct clk clk_h = {
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.name = "hclk",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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};
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static struct clk clk_p = {
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.name = "pclk",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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};
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/* clocks that could be registered by external code */
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struct clk s3c24xx_dclk0 = {
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.name = "dclk0",
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.id = -1,
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};
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struct clk s3c24xx_dclk1 = {
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.name = "dclk1",
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.id = -1,
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};
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struct clk s3c24xx_clkout0 = {
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.name = "clkout0",
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.id = -1,
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};
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struct clk s3c24xx_clkout1 = {
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.name = "clkout1",
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.id = -1,
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};
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struct clk s3c24xx_uclk = {
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.name = "uclk",
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.id = -1,
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};
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/* clock definitions */
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static struct clk init_clocks[] = {
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{ .name = "nand",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_NAND
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},
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{ .name = "lcd",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_LCDC
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},
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{ .name = "usb-host",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_USBH
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},
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{ .name = "usb-device",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_USBD
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},
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{ .name = "timers",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_PWMT
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},
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{ .name = "sdi",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_SDI
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},
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{ .name = "uart",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART0
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},
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{ .name = "uart",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART1
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},
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{ .name = "uart",
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.id = 2,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART2
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},
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{ .name = "gpio",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_GPIO
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},
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{ .name = "rtc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_RTC
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},
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{ .name = "adc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_ADC
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},
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{ .name = "i2c",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_IIC
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},
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{ .name = "iis",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_IIS
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},
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{ .name = "spi",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_SPI
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},
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{ .name = "watchdog",
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.id = -1,
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.parent = &clk_p,
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.ctrlbit = 0
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}
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};
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/* initialise the clock system */
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int s3c24xx_register_clock(struct clk *clk)
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{
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clk->owner = THIS_MODULE;
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atomic_set(&clk->used, 0);
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if (clk->enable == NULL)
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clk->enable = clk_null_enable;
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/* add to the list of available clocks */
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down(&clocks_sem);
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list_add(&clk->list, &clocks);
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up(&clocks_sem);
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return 0;
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}
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/* initalise all the clocks */
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int __init s3c24xx_setup_clocks(unsigned long xtal,
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unsigned long fclk,
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unsigned long hclk,
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unsigned long pclk)
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{
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struct clk *clkp = init_clocks;
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int ptr;
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int ret;
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printk(KERN_INFO "S3C2410 Clocks, (c) 2004 Simtec Electronics\n");
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/* initialise the main system clocks */
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clk_xtal.rate = xtal;
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clk_h.rate = hclk;
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clk_p.rate = pclk;
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clk_f.rate = fclk;
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/* it looks like just setting the register here is not good
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* enough, and causes the odd hang at initial boot time, so
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* do all of them indivdually.
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*
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* I think disabling the LCD clock if the LCD is active is
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* very dangerous, and therefore the bootloader should be
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* careful to not enable the LCD clock if it is not needed.
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*
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* and of course, this looks neater
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*/
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s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
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s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
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s3c24xx_clk_enable(S3C2410_CLKCON_USBD, 0);
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s3c24xx_clk_enable(S3C2410_CLKCON_ADC, 0);
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s3c24xx_clk_enable(S3C2410_CLKCON_IIC, 0);
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s3c24xx_clk_enable(S3C2410_CLKCON_SPI, 0);
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/* assume uart clocks are correctly setup */
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/* register our clocks */
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if (s3c24xx_register_clock(&clk_xtal) < 0)
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printk(KERN_ERR "failed to register master xtal\n");
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if (s3c24xx_register_clock(&clk_f) < 0)
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printk(KERN_ERR "failed to register cpu fclk\n");
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if (s3c24xx_register_clock(&clk_h) < 0)
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printk(KERN_ERR "failed to register cpu hclk\n");
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if (s3c24xx_register_clock(&clk_p) < 0)
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printk(KERN_ERR "failed to register cpu pclk\n");
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/* register clocks from clock array */
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for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
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ret = s3c24xx_register_clock(clkp);
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if (ret < 0) {
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printk(KERN_ERR "Failed to register clock %s (%d)\n",
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clkp->name, ret);
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}
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}
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return 0;
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}
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/* S3C2440 extended clock support */
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#ifdef CONFIG_CPU_S3C2440
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static struct clk s3c2440_clk_upll = {
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.name = "upll",
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.id = -1,
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};
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static struct clk s3c2440_clk_cam = {
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.name = "camif",
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.parent = &clk_h,
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.id = -1,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2440_CLKCON_CAMERA,
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};
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static struct clk s3c2440_clk_ac97 = {
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.name = "ac97",
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.parent = &clk_p,
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.id = -1,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2440_CLKCON_CAMERA,
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};
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static int s3c2440_clk_add(struct sys_device *sysdev)
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{
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unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
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s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate);
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printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n",
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print_mhz(s3c2440_clk_upll.rate));
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s3c24xx_register_clock(&s3c2440_clk_ac97);
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s3c24xx_register_clock(&s3c2440_clk_cam);
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s3c24xx_register_clock(&s3c2440_clk_upll);
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clk_disable(&s3c2440_clk_ac97);
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clk_disable(&s3c2440_clk_cam);
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return 0;
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}
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static struct sysdev_driver s3c2440_clk_driver = {
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.add = s3c2440_clk_add,
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};
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static int s3c24xx_clk_driver(void)
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{
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return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
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}
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arch_initcall(s3c24xx_clk_driver);
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#endif /* CONFIG_CPU_S3C2440 */
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