![Linus Torvalds](/assets/img/avatar_default.png)
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
1323 lines
28 KiB
C
1323 lines
28 KiB
C
/*
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* cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
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*
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* MIPS floating point support
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* Copyright (C) 1994-2000 Algorithmics Ltd.
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* http://www.algor.co.uk
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*
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* A complete emulator for MIPS coprocessor 1 instructions. This is
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* required for #float(switch) or #float(trap), where it catches all
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* COP1 instructions via the "CoProcessor Unusable" exception.
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*
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* More surprisingly it is also required for #float(ieee), to help out
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* the hardware fpu at the boundaries of the IEEE-754 representation
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* (denormalised values, infinities, underflow, etc). It is made
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* quite nasty because emulation of some non-COP1 instructions is
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* required, e.g. in branch delay slots.
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*
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* Note if you know that you won't have an fpu, then you'll get much
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* better performance by compiling with -msoft-float!
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*/
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#include <linux/sched.h>
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#include <asm/inst.h>
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#include <asm/bootinfo.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/signal.h>
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#include <asm/mipsregs.h>
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#include <asm/fpu_emulator.h>
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#include <asm/uaccess.h>
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#include <asm/branch.h>
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#include "ieee754.h"
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#include "dsemul.h"
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/* Strap kernel emulator for full MIPS IV emulation */
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#ifdef __mips
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#undef __mips
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#endif
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#define __mips 4
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/* Function which emulates a floating point instruction. */
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static int fpu_emu(struct pt_regs *, struct mips_fpu_soft_struct *,
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mips_instruction);
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#if __mips >= 4 && __mips != 32
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static int fpux_emu(struct pt_regs *,
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struct mips_fpu_soft_struct *, mips_instruction);
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#endif
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/* Further private data for which no space exists in mips_fpu_soft_struct */
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struct mips_fpu_emulator_private fpuemuprivate;
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/* Control registers */
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#define FPCREG_RID 0 /* $0 = revision id */
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#define FPCREG_CSR 31 /* $31 = csr */
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/* Convert Mips rounding mode (0..3) to IEEE library modes. */
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static const unsigned char ieee_rm[4] = {
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IEEE754_RN, IEEE754_RZ, IEEE754_RU, IEEE754_RD
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};
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#if __mips >= 4
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/* convert condition code register number to csr bit */
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static const unsigned int fpucondbit[8] = {
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FPU_CSR_COND0,
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FPU_CSR_COND1,
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FPU_CSR_COND2,
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FPU_CSR_COND3,
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FPU_CSR_COND4,
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FPU_CSR_COND5,
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FPU_CSR_COND6,
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FPU_CSR_COND7
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};
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#endif
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/*
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* Redundant with logic already in kernel/branch.c,
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* embedded in compute_return_epc. At some point,
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* a single subroutine should be used across both
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* modules.
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*/
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static int isBranchInstr(mips_instruction * i)
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{
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switch (MIPSInst_OPCODE(*i)) {
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case spec_op:
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switch (MIPSInst_FUNC(*i)) {
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case jalr_op:
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case jr_op:
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return 1;
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}
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break;
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case bcond_op:
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switch (MIPSInst_RT(*i)) {
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case bltz_op:
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case bgez_op:
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case bltzl_op:
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case bgezl_op:
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case bltzal_op:
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case bgezal_op:
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case bltzall_op:
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case bgezall_op:
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return 1;
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}
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break;
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case j_op:
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case jal_op:
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case jalx_op:
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case beq_op:
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case bne_op:
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case blez_op:
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case bgtz_op:
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case beql_op:
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case bnel_op:
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case blezl_op:
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case bgtzl_op:
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return 1;
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case cop0_op:
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case cop1_op:
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case cop2_op:
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case cop1x_op:
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if (MIPSInst_RS(*i) == bc_op)
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return 1;
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break;
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}
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return 0;
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}
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/*
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* In the Linux kernel, we support selection of FPR format on the
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* basis of the Status.FR bit. This does imply that, if a full 32
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* FPRs are desired, there needs to be a flip-flop that can be written
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* to one at that bit position. In any case, O32 MIPS ABI uses
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* only the even FPRs (Status.FR = 0).
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*/
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#define CP0_STATUS_FR_SUPPORT
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#ifdef CP0_STATUS_FR_SUPPORT
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#define FR_BIT ST0_FR
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#else
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#define FR_BIT 0
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#endif
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#define SIFROMREG(si,x) ((si) = \
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(xcp->cp0_status & FR_BIT) || !(x & 1) ? \
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(int)ctx->fpr[x] : \
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(int)(ctx->fpr[x & ~1] >> 32 ))
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#define SITOREG(si,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \
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(xcp->cp0_status & FR_BIT) || !(x & 1) ? \
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ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
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ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
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#define DIFROMREG(di,x) ((di) = \
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ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)])
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#define DITOREG(di,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
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= (di))
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#define SPFROMREG(sp,x) SIFROMREG((sp).bits,x)
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#define SPTOREG(sp,x) SITOREG((sp).bits,x)
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#define DPFROMREG(dp,x) DIFROMREG((dp).bits,x)
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#define DPTOREG(dp,x) DITOREG((dp).bits,x)
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/*
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* Emulate the single floating point instruction pointed at by EPC.
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* Two instructions if the instruction is in a branch delay slot.
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*/
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static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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{
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mips_instruction ir;
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vaddr_t emulpc, contpc;
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unsigned int cond;
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if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) {
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fpuemuprivate.stats.errors++;
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return SIGBUS;
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}
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/* XXX NEC Vr54xx bug workaround */
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if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
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xcp->cp0_cause &= ~CAUSEF_BD;
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if (xcp->cp0_cause & CAUSEF_BD) {
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/*
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* The instruction to be emulated is in a branch delay slot
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* which means that we have to emulate the branch instruction
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* BEFORE we do the cop1 instruction.
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*
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* This branch could be a COP1 branch, but in that case we
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* would have had a trap for that instruction, and would not
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* come through this route.
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*
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* Linux MIPS branch emulator operates on context, updating the
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* cp0_epc.
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*/
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emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */
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if (__compute_return_epc(xcp)) {
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#ifdef CP1DBG
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printk("failed to emulate branch at %p\n",
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REG_TO_VA(xcp->cp0_epc));
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#endif
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return SIGILL;
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}
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if (get_user(ir, (mips_instruction *) emulpc)) {
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fpuemuprivate.stats.errors++;
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return SIGBUS;
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}
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/* __compute_return_epc() will have updated cp0_epc */
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contpc = REG_TO_VA xcp->cp0_epc;
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/* In order not to confuse ptrace() et al, tweak context */
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xcp->cp0_epc = VA_TO_REG emulpc - 4;
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}
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else {
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emulpc = REG_TO_VA xcp->cp0_epc;
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contpc = REG_TO_VA(xcp->cp0_epc + 4);
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}
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emul:
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fpuemuprivate.stats.emulated++;
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switch (MIPSInst_OPCODE(ir)) {
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#ifndef SINGLE_ONLY_FPU
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case ldc1_op:{
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u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
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MIPSInst_SIMM(ir));
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u64 val;
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fpuemuprivate.stats.loads++;
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if (get_user(val, va)) {
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fpuemuprivate.stats.errors++;
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return SIGBUS;
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}
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DITOREG(val, MIPSInst_RT(ir));
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break;
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}
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case sdc1_op:{
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u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
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MIPSInst_SIMM(ir));
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u64 val;
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fpuemuprivate.stats.stores++;
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DIFROMREG(val, MIPSInst_RT(ir));
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if (put_user(val, va)) {
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fpuemuprivate.stats.errors++;
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return SIGBUS;
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}
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break;
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}
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#endif
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case lwc1_op:{
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u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
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MIPSInst_SIMM(ir));
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u32 val;
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fpuemuprivate.stats.loads++;
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if (get_user(val, va)) {
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fpuemuprivate.stats.errors++;
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return SIGBUS;
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}
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#ifdef SINGLE_ONLY_FPU
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if (MIPSInst_RT(ir) & 1) {
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/* illegal register in single-float mode */
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return SIGILL;
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}
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#endif
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SITOREG(val, MIPSInst_RT(ir));
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break;
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}
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case swc1_op:{
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u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
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MIPSInst_SIMM(ir));
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u32 val;
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fpuemuprivate.stats.stores++;
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#ifdef SINGLE_ONLY_FPU
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if (MIPSInst_RT(ir) & 1) {
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/* illegal register in single-float mode */
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return SIGILL;
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}
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#endif
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SIFROMREG(val, MIPSInst_RT(ir));
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if (put_user(val, va)) {
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fpuemuprivate.stats.errors++;
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return SIGBUS;
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}
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break;
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}
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case cop1_op:
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switch (MIPSInst_RS(ir)) {
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#if __mips64 && !defined(SINGLE_ONLY_FPU)
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case dmfc_op:
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/* copregister fs -> gpr[rt] */
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if (MIPSInst_RT(ir) != 0) {
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DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
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MIPSInst_RD(ir));
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}
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break;
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case dmtc_op:
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/* copregister fs <- rt */
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DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
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break;
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#endif
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case mfc_op:
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/* copregister rd -> gpr[rt] */
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#ifdef SINGLE_ONLY_FPU
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if (MIPSInst_RD(ir) & 1) {
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/* illegal register in single-float mode */
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return SIGILL;
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}
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#endif
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if (MIPSInst_RT(ir) != 0) {
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SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
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MIPSInst_RD(ir));
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}
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break;
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case mtc_op:
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/* copregister rd <- rt */
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#ifdef SINGLE_ONLY_FPU
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if (MIPSInst_RD(ir) & 1) {
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/* illegal register in single-float mode */
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return SIGILL;
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}
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#endif
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SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
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break;
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case cfc_op:{
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/* cop control register rd -> gpr[rt] */
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u32 value;
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if (ir == CP1UNDEF) {
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return do_dsemulret(xcp);
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}
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if (MIPSInst_RD(ir) == FPCREG_CSR) {
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value = ctx->fcr31;
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#ifdef CSRTRACE
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printk("%p gpr[%d]<-csr=%08x\n",
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REG_TO_VA(xcp->cp0_epc),
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MIPSInst_RT(ir), value);
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#endif
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}
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else if (MIPSInst_RD(ir) == FPCREG_RID)
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value = 0;
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else
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value = 0;
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if (MIPSInst_RT(ir))
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xcp->regs[MIPSInst_RT(ir)] = value;
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break;
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}
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case ctc_op:{
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/* copregister rd <- rt */
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u32 value;
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if (MIPSInst_RT(ir) == 0)
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value = 0;
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else
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value = xcp->regs[MIPSInst_RT(ir)];
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|
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/* we only have one writable control reg
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*/
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if (MIPSInst_RD(ir) == FPCREG_CSR) {
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#ifdef CSRTRACE
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printk("%p gpr[%d]->csr=%08x\n",
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REG_TO_VA(xcp->cp0_epc),
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MIPSInst_RT(ir), value);
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#endif
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ctx->fcr31 = value;
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/* copy new rounding mode and
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flush bit to ieee library state! */
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ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0;
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ieee754_csr.rm = ieee_rm[value & 0x3];
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}
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if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
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return SIGFPE;
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}
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break;
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}
|
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|
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case bc_op:{
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int likely = 0;
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if (xcp->cp0_cause & CAUSEF_BD)
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return SIGILL;
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|
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#if __mips >= 4
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cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
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#else
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cond = ctx->fcr31 & FPU_CSR_COND;
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#endif
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switch (MIPSInst_RT(ir) & 3) {
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case bcfl_op:
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likely = 1;
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case bcf_op:
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cond = !cond;
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break;
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case bctl_op:
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likely = 1;
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case bct_op:
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break;
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default:
|
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/* thats an illegal instruction */
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return SIGILL;
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}
|
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|
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xcp->cp0_cause |= CAUSEF_BD;
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if (cond) {
|
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/* branch taken: emulate dslot
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* instruction
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*/
|
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xcp->cp0_epc += 4;
|
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contpc = REG_TO_VA
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(xcp->cp0_epc +
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(MIPSInst_SIMM(ir) << 2));
|
|
|
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if (get_user(ir, (mips_instruction *)
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REG_TO_VA xcp->cp0_epc)) {
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fpuemuprivate.stats.errors++;
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return SIGBUS;
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}
|
|
|
|
switch (MIPSInst_OPCODE(ir)) {
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case lwc1_op:
|
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case swc1_op:
|
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#if (__mips >= 2 || __mips64) && !defined(SINGLE_ONLY_FPU)
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case ldc1_op:
|
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case sdc1_op:
|
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#endif
|
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case cop1_op:
|
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#if __mips >= 4 && __mips != 32
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case cop1x_op:
|
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#endif
|
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/* its one of ours */
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goto emul;
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|
#if __mips >= 4
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case spec_op:
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|
if (MIPSInst_FUNC(ir) == movc_op)
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goto emul;
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|
break;
|
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#endif
|
|
}
|
|
|
|
/*
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* Single step the non-cp1
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* instruction in the dslot
|
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*/
|
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return mips_dsemul(xcp, ir, VA_TO_REG contpc);
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}
|
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else {
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/* branch not taken */
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if (likely) {
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/*
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* branch likely nullifies
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* dslot if not taken
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*/
|
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xcp->cp0_epc += 4;
|
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contpc += 4;
|
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/*
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* else continue & execute
|
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* dslot as normal insn
|
|
*/
|
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}
|
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}
|
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break;
|
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}
|
|
|
|
default:
|
|
if (!(MIPSInst_RS(ir) & 0x10))
|
|
return SIGILL;
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|
{
|
|
int sig;
|
|
|
|
/* a real fpu computation instruction */
|
|
if ((sig = fpu_emu(xcp, ctx, ir)))
|
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return sig;
|
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}
|
|
}
|
|
break;
|
|
|
|
#if __mips >= 4 && __mips != 32
|
|
case cop1x_op:{
|
|
int sig;
|
|
|
|
if ((sig = fpux_emu(xcp, ctx, ir)))
|
|
return sig;
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
#if __mips >= 4
|
|
case spec_op:
|
|
if (MIPSInst_FUNC(ir) != movc_op)
|
|
return SIGILL;
|
|
cond = fpucondbit[MIPSInst_RT(ir) >> 2];
|
|
if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
|
|
xcp->regs[MIPSInst_RD(ir)] =
|
|
xcp->regs[MIPSInst_RS(ir)];
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
/* we did it !! */
|
|
xcp->cp0_epc = VA_TO_REG(contpc);
|
|
xcp->cp0_cause &= ~CAUSEF_BD;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Conversion table from MIPS compare ops 48-63
|
|
* cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
|
|
*/
|
|
static const unsigned char cmptab[8] = {
|
|
0, /* cmp_0 (sig) cmp_sf */
|
|
IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
|
|
IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
|
|
IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
|
|
IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
|
|
IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
|
|
IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
|
|
IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
|
|
};
|
|
|
|
|
|
#if __mips >= 4 && __mips != 32
|
|
|
|
/*
|
|
* Additional MIPS4 instructions
|
|
*/
|
|
|
|
#define DEF3OP(name, p, f1, f2, f3) \
|
|
static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \
|
|
ieee754##p t) \
|
|
{ \
|
|
struct ieee754_csr ieee754_csr_save; \
|
|
s = f1 (s, t); \
|
|
ieee754_csr_save = ieee754_csr; \
|
|
s = f2 (s, r); \
|
|
ieee754_csr_save.cx |= ieee754_csr.cx; \
|
|
ieee754_csr_save.sx |= ieee754_csr.sx; \
|
|
s = f3 (s); \
|
|
ieee754_csr.cx |= ieee754_csr_save.cx; \
|
|
ieee754_csr.sx |= ieee754_csr_save.sx; \
|
|
return s; \
|
|
}
|
|
|
|
static ieee754dp fpemu_dp_recip(ieee754dp d)
|
|
{
|
|
return ieee754dp_div(ieee754dp_one(0), d);
|
|
}
|
|
|
|
static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
|
|
{
|
|
return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
|
|
}
|
|
|
|
static ieee754sp fpemu_sp_recip(ieee754sp s)
|
|
{
|
|
return ieee754sp_div(ieee754sp_one(0), s);
|
|
}
|
|
|
|
static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
|
|
{
|
|
return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
|
|
}
|
|
|
|
DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add,);
|
|
DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub,);
|
|
DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
|
|
DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
|
|
DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add,);
|
|
DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,);
|
|
DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
|
|
DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
|
|
|
|
static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
|
|
mips_instruction ir)
|
|
{
|
|
unsigned rcsr = 0; /* resulting csr */
|
|
|
|
fpuemuprivate.stats.cp1xops++;
|
|
|
|
switch (MIPSInst_FMA_FFMT(ir)) {
|
|
case s_fmt:{ /* 0 */
|
|
|
|
ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
|
|
ieee754sp fd, fr, fs, ft;
|
|
u32 *va;
|
|
u32 val;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case lwxc1_op:
|
|
va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
fpuemuprivate.stats.loads++;
|
|
if (get_user(val, va)) {
|
|
fpuemuprivate.stats.errors++;
|
|
return SIGBUS;
|
|
}
|
|
#ifdef SINGLE_ONLY_FPU
|
|
if (MIPSInst_FD(ir) & 1) {
|
|
/* illegal register in single-float
|
|
* mode
|
|
*/
|
|
return SIGILL;
|
|
}
|
|
#endif
|
|
SITOREG(val, MIPSInst_FD(ir));
|
|
break;
|
|
|
|
case swxc1_op:
|
|
va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
fpuemuprivate.stats.stores++;
|
|
#ifdef SINGLE_ONLY_FPU
|
|
if (MIPSInst_FS(ir) & 1) {
|
|
/* illegal register in single-float
|
|
* mode
|
|
*/
|
|
return SIGILL;
|
|
}
|
|
#endif
|
|
|
|
SIFROMREG(val, MIPSInst_FS(ir));
|
|
if (put_user(val, va)) {
|
|
fpuemuprivate.stats.errors++;
|
|
return SIGBUS;
|
|
}
|
|
break;
|
|
|
|
case madd_s_op:
|
|
handler = fpemu_sp_madd;
|
|
goto scoptop;
|
|
case msub_s_op:
|
|
handler = fpemu_sp_msub;
|
|
goto scoptop;
|
|
case nmadd_s_op:
|
|
handler = fpemu_sp_nmadd;
|
|
goto scoptop;
|
|
case nmsub_s_op:
|
|
handler = fpemu_sp_nmsub;
|
|
goto scoptop;
|
|
|
|
scoptop:
|
|
SPFROMREG(fr, MIPSInst_FR(ir));
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
fd = (*handler) (fr, fs, ft);
|
|
SPTOREG(fd, MIPSInst_FD(ir));
|
|
|
|
copcsr:
|
|
if (ieee754_cxtest(IEEE754_INEXACT))
|
|
rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
|
|
if (ieee754_cxtest(IEEE754_UNDERFLOW))
|
|
rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
|
|
if (ieee754_cxtest(IEEE754_OVERFLOW))
|
|
rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
|
|
if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
|
|
rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
|
|
ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
|
|
if (ieee754_csr.nod)
|
|
ctx->fcr31 |= 0x1000000;
|
|
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
|
|
/*printk ("SIGFPE: fpu csr = %08x\n",
|
|
ctx->fcr31); */
|
|
return SIGFPE;
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
|
|
#ifndef SINGLE_ONLY_FPU
|
|
case d_fmt:{ /* 1 */
|
|
ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
|
|
ieee754dp fd, fr, fs, ft;
|
|
u64 *va;
|
|
u64 val;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case ldxc1_op:
|
|
va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
fpuemuprivate.stats.loads++;
|
|
if (get_user(val, va)) {
|
|
fpuemuprivate.stats.errors++;
|
|
return SIGBUS;
|
|
}
|
|
DITOREG(val, MIPSInst_FD(ir));
|
|
break;
|
|
|
|
case sdxc1_op:
|
|
va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
fpuemuprivate.stats.stores++;
|
|
DIFROMREG(val, MIPSInst_FS(ir));
|
|
if (put_user(val, va)) {
|
|
fpuemuprivate.stats.errors++;
|
|
return SIGBUS;
|
|
}
|
|
break;
|
|
|
|
case madd_d_op:
|
|
handler = fpemu_dp_madd;
|
|
goto dcoptop;
|
|
case msub_d_op:
|
|
handler = fpemu_dp_msub;
|
|
goto dcoptop;
|
|
case nmadd_d_op:
|
|
handler = fpemu_dp_nmadd;
|
|
goto dcoptop;
|
|
case nmsub_d_op:
|
|
handler = fpemu_dp_nmsub;
|
|
goto dcoptop;
|
|
|
|
dcoptop:
|
|
DPFROMREG(fr, MIPSInst_FR(ir));
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
fd = (*handler) (fr, fs, ft);
|
|
DPTOREG(fd, MIPSInst_FD(ir));
|
|
goto copcsr;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
case 0x7: /* 7 */
|
|
if (MIPSInst_FUNC(ir) != pfetch_op) {
|
|
return SIGILL;
|
|
}
|
|
/* ignore prefx operation */
|
|
break;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
* Emulate a single COP1 arithmetic instruction.
|
|
*/
|
|
static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
|
|
mips_instruction ir)
|
|
{
|
|
int rfmt; /* resulting format */
|
|
unsigned rcsr = 0; /* resulting csr */
|
|
unsigned cond;
|
|
union {
|
|
ieee754dp d;
|
|
ieee754sp s;
|
|
int w;
|
|
#if __mips64
|
|
s64 l;
|
|
#endif
|
|
} rv; /* resulting value */
|
|
|
|
fpuemuprivate.stats.cp1ops++;
|
|
switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
|
|
case s_fmt:{ /* 0 */
|
|
union {
|
|
ieee754sp(*b) (ieee754sp, ieee754sp);
|
|
ieee754sp(*u) (ieee754sp);
|
|
} handler;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
/* binary ops */
|
|
case fadd_op:
|
|
handler.b = ieee754sp_add;
|
|
goto scopbop;
|
|
case fsub_op:
|
|
handler.b = ieee754sp_sub;
|
|
goto scopbop;
|
|
case fmul_op:
|
|
handler.b = ieee754sp_mul;
|
|
goto scopbop;
|
|
case fdiv_op:
|
|
handler.b = ieee754sp_div;
|
|
goto scopbop;
|
|
|
|
/* unary ops */
|
|
#if __mips >= 2 || __mips64
|
|
case fsqrt_op:
|
|
handler.u = ieee754sp_sqrt;
|
|
goto scopuop;
|
|
#endif
|
|
#if __mips >= 4 && __mips != 32
|
|
case frsqrt_op:
|
|
handler.u = fpemu_sp_rsqrt;
|
|
goto scopuop;
|
|
case frecip_op:
|
|
handler.u = fpemu_sp_recip;
|
|
goto scopuop;
|
|
#endif
|
|
#if __mips >= 4
|
|
case fmovc_op:
|
|
cond = fpucondbit[MIPSInst_FT(ir) >> 2];
|
|
if (((ctx->fcr31 & cond) != 0) !=
|
|
((MIPSInst_FT(ir) & 1) != 0))
|
|
return 0;
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
case fmovz_op:
|
|
if (xcp->regs[MIPSInst_FT(ir)] != 0)
|
|
return 0;
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
case fmovn_op:
|
|
if (xcp->regs[MIPSInst_FT(ir)] == 0)
|
|
return 0;
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
#endif
|
|
case fabs_op:
|
|
handler.u = ieee754sp_abs;
|
|
goto scopuop;
|
|
case fneg_op:
|
|
handler.u = ieee754sp_neg;
|
|
goto scopuop;
|
|
case fmov_op:
|
|
/* an easy one */
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
goto copcsr;
|
|
|
|
/* binary op on handler */
|
|
scopbop:
|
|
{
|
|
ieee754sp fs, ft;
|
|
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
|
|
rv.s = (*handler.b) (fs, ft);
|
|
goto copcsr;
|
|
}
|
|
scopuop:
|
|
{
|
|
ieee754sp fs;
|
|
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = (*handler.u) (fs);
|
|
goto copcsr;
|
|
}
|
|
copcsr:
|
|
if (ieee754_cxtest(IEEE754_INEXACT))
|
|
rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
|
|
if (ieee754_cxtest(IEEE754_UNDERFLOW))
|
|
rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
|
|
if (ieee754_cxtest(IEEE754_OVERFLOW))
|
|
rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
|
|
if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
|
|
rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
|
|
if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
|
|
rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
break;
|
|
|
|
/* unary conv ops */
|
|
case fcvts_op:
|
|
return SIGILL; /* not defined */
|
|
case fcvtd_op:{
|
|
#ifdef SINGLE_ONLY_FPU
|
|
return SIGILL; /* not defined */
|
|
#else
|
|
ieee754sp fs;
|
|
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_fsp(fs);
|
|
rfmt = d_fmt;
|
|
goto copcsr;
|
|
}
|
|
#endif
|
|
case fcvtw_op:{
|
|
ieee754sp fs;
|
|
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.w = ieee754sp_tint(fs);
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
}
|
|
|
|
#if __mips >= 2 || __mips64
|
|
case fround_op:
|
|
case ftrunc_op:
|
|
case fceil_op:
|
|
case ffloor_op:{
|
|
unsigned int oldrm = ieee754_csr.rm;
|
|
ieee754sp fs;
|
|
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
|
|
rv.w = ieee754sp_tint(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
}
|
|
#endif /* __mips >= 2 */
|
|
|
|
#if __mips64 && !defined(SINGLE_ONLY_FPU)
|
|
case fcvtl_op:{
|
|
ieee754sp fs;
|
|
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.l = ieee754sp_tlong(fs);
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
}
|
|
|
|
case froundl_op:
|
|
case ftruncl_op:
|
|
case fceill_op:
|
|
case ffloorl_op:{
|
|
unsigned int oldrm = ieee754_csr.rm;
|
|
ieee754sp fs;
|
|
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
|
|
rv.l = ieee754sp_tlong(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
}
|
|
#endif /* __mips64 && !fpu(single) */
|
|
|
|
default:
|
|
if (MIPSInst_FUNC(ir) >= fcmp_op) {
|
|
unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
|
|
ieee754sp fs, ft;
|
|
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
rv.w = ieee754sp_cmp(fs, ft,
|
|
cmptab[cmpop & 0x7], cmpop & 0x8);
|
|
rfmt = -1;
|
|
if ((cmpop & 0x8) && ieee754_cxtest
|
|
(IEEE754_INVALID_OPERATION))
|
|
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
else
|
|
goto copcsr;
|
|
|
|
}
|
|
else {
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
#ifndef SINGLE_ONLY_FPU
|
|
case d_fmt:{
|
|
union {
|
|
ieee754dp(*b) (ieee754dp, ieee754dp);
|
|
ieee754dp(*u) (ieee754dp);
|
|
} handler;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
/* binary ops */
|
|
case fadd_op:
|
|
handler.b = ieee754dp_add;
|
|
goto dcopbop;
|
|
case fsub_op:
|
|
handler.b = ieee754dp_sub;
|
|
goto dcopbop;
|
|
case fmul_op:
|
|
handler.b = ieee754dp_mul;
|
|
goto dcopbop;
|
|
case fdiv_op:
|
|
handler.b = ieee754dp_div;
|
|
goto dcopbop;
|
|
|
|
/* unary ops */
|
|
#if __mips >= 2 || __mips64
|
|
case fsqrt_op:
|
|
handler.u = ieee754dp_sqrt;
|
|
goto dcopuop;
|
|
#endif
|
|
#if __mips >= 4 && __mips != 32
|
|
case frsqrt_op:
|
|
handler.u = fpemu_dp_rsqrt;
|
|
goto dcopuop;
|
|
case frecip_op:
|
|
handler.u = fpemu_dp_recip;
|
|
goto dcopuop;
|
|
#endif
|
|
#if __mips >= 4
|
|
case fmovc_op:
|
|
cond = fpucondbit[MIPSInst_FT(ir) >> 2];
|
|
if (((ctx->fcr31 & cond) != 0) !=
|
|
((MIPSInst_FT(ir) & 1) != 0))
|
|
return 0;
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
case fmovz_op:
|
|
if (xcp->regs[MIPSInst_FT(ir)] != 0)
|
|
return 0;
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
case fmovn_op:
|
|
if (xcp->regs[MIPSInst_FT(ir)] == 0)
|
|
return 0;
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
#endif
|
|
case fabs_op:
|
|
handler.u = ieee754dp_abs;
|
|
goto dcopuop;
|
|
|
|
case fneg_op:
|
|
handler.u = ieee754dp_neg;
|
|
goto dcopuop;
|
|
|
|
case fmov_op:
|
|
/* an easy one */
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
goto copcsr;
|
|
|
|
/* binary op on handler */
|
|
dcopbop:{
|
|
ieee754dp fs, ft;
|
|
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
|
|
rv.d = (*handler.b) (fs, ft);
|
|
goto copcsr;
|
|
}
|
|
dcopuop:{
|
|
ieee754dp fs;
|
|
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = (*handler.u) (fs);
|
|
goto copcsr;
|
|
}
|
|
|
|
/* unary conv ops */
|
|
case fcvts_op:{
|
|
ieee754dp fs;
|
|
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_fdp(fs);
|
|
rfmt = s_fmt;
|
|
goto copcsr;
|
|
}
|
|
case fcvtd_op:
|
|
return SIGILL; /* not defined */
|
|
|
|
case fcvtw_op:{
|
|
ieee754dp fs;
|
|
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.w = ieee754dp_tint(fs); /* wrong */
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
}
|
|
|
|
#if __mips >= 2 || __mips64
|
|
case fround_op:
|
|
case ftrunc_op:
|
|
case fceil_op:
|
|
case ffloor_op:{
|
|
unsigned int oldrm = ieee754_csr.rm;
|
|
ieee754dp fs;
|
|
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
|
|
rv.w = ieee754dp_tint(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
}
|
|
#endif
|
|
|
|
#if __mips64 && !defined(SINGLE_ONLY_FPU)
|
|
case fcvtl_op:{
|
|
ieee754dp fs;
|
|
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.l = ieee754dp_tlong(fs);
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
}
|
|
|
|
case froundl_op:
|
|
case ftruncl_op:
|
|
case fceill_op:
|
|
case ffloorl_op:{
|
|
unsigned int oldrm = ieee754_csr.rm;
|
|
ieee754dp fs;
|
|
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
|
|
rv.l = ieee754dp_tlong(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
}
|
|
#endif /* __mips >= 3 && !fpu(single) */
|
|
|
|
default:
|
|
if (MIPSInst_FUNC(ir) >= fcmp_op) {
|
|
unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
|
|
ieee754dp fs, ft;
|
|
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
rv.w = ieee754dp_cmp(fs, ft,
|
|
cmptab[cmpop & 0x7], cmpop & 0x8);
|
|
rfmt = -1;
|
|
if ((cmpop & 0x8)
|
|
&&
|
|
ieee754_cxtest
|
|
(IEEE754_INVALID_OPERATION))
|
|
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
else
|
|
goto copcsr;
|
|
|
|
}
|
|
else {
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
#endif /* ifndef SINGLE_ONLY_FPU */
|
|
|
|
case w_fmt:{
|
|
ieee754sp fs;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case fcvts_op:
|
|
/* convert word to single precision real */
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_fint(fs.bits);
|
|
rfmt = s_fmt;
|
|
goto copcsr;
|
|
#ifndef SINGLE_ONLY_FPU
|
|
case fcvtd_op:
|
|
/* convert word to double precision real */
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_fint(fs.bits);
|
|
rfmt = d_fmt;
|
|
goto copcsr;
|
|
#endif
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
|
|
#if __mips64 && !defined(SINGLE_ONLY_FPU)
|
|
case l_fmt:{
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case fcvts_op:
|
|
/* convert long to single precision real */
|
|
rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
|
|
rfmt = s_fmt;
|
|
goto copcsr;
|
|
case fcvtd_op:
|
|
/* convert long to double precision real */
|
|
rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
|
|
rfmt = d_fmt;
|
|
goto copcsr;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
/*
|
|
* Update the fpu CSR register for this operation.
|
|
* If an exception is required, generate a tidy SIGFPE exception,
|
|
* without updating the result register.
|
|
* Note: cause exception bits do not accumulate, they are rewritten
|
|
* for each op; only the flag/sticky bits accumulate.
|
|
*/
|
|
ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
|
|
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
|
|
/*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
|
|
return SIGFPE;
|
|
}
|
|
|
|
/*
|
|
* Now we can safely write the result back to the register file.
|
|
*/
|
|
switch (rfmt) {
|
|
case -1:{
|
|
#if __mips >= 4
|
|
cond = fpucondbit[MIPSInst_FD(ir) >> 2];
|
|
#else
|
|
cond = FPU_CSR_COND;
|
|
#endif
|
|
if (rv.w)
|
|
ctx->fcr31 |= cond;
|
|
else
|
|
ctx->fcr31 &= ~cond;
|
|
break;
|
|
}
|
|
#ifndef SINGLE_ONLY_FPU
|
|
case d_fmt:
|
|
DPTOREG(rv.d, MIPSInst_FD(ir));
|
|
break;
|
|
#endif
|
|
case s_fmt:
|
|
SPTOREG(rv.s, MIPSInst_FD(ir));
|
|
break;
|
|
case w_fmt:
|
|
SITOREG(rv.w, MIPSInst_FD(ir));
|
|
break;
|
|
#if __mips64 && !defined(SINGLE_ONLY_FPU)
|
|
case l_fmt:
|
|
DITOREG(rv.l, MIPSInst_FD(ir));
|
|
break;
|
|
#endif
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
|
|
struct mips_fpu_soft_struct *ctx)
|
|
{
|
|
gpreg_t oldepc, prevepc;
|
|
mips_instruction insn;
|
|
int sig = 0;
|
|
|
|
oldepc = xcp->cp0_epc;
|
|
do {
|
|
prevepc = xcp->cp0_epc;
|
|
|
|
if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) {
|
|
fpuemuprivate.stats.errors++;
|
|
return SIGBUS;
|
|
}
|
|
if (insn == 0)
|
|
xcp->cp0_epc += 4; /* skip nops */
|
|
else {
|
|
/* Update ieee754_csr. Only relevant if we have a
|
|
h/w FPU */
|
|
ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0;
|
|
ieee754_csr.rm = ieee_rm[ctx->fcr31 & 0x3];
|
|
ieee754_csr.cx = (ctx->fcr31 >> 12) & 0x1f;
|
|
sig = cop1Emulate(xcp, ctx);
|
|
}
|
|
|
|
if (cpu_has_fpu)
|
|
break;
|
|
if (sig)
|
|
break;
|
|
|
|
cond_resched();
|
|
} while (xcp->cp0_epc > prevepc);
|
|
|
|
/* SIGILL indicates a non-fpu instruction */
|
|
if (sig == SIGILL && xcp->cp0_epc != oldepc)
|
|
/* but if epc has advanced, then ignore it */
|
|
sig = 0;
|
|
|
|
return sig;
|
|
}
|