![Pratyush Anand](/assets/img/avatar_default.png)
This patch adds support for uprobe on ARM64 architecture. Unit tests for following have been done so far and they have been found working 1. Step-able instructions, like sub, ldr, add etc. 2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases Currently it does not support aarch32 instruction probing. Signed-off-by: Pratyush Anand <panand@redhat.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
155 lines
4.9 KiB
C
155 lines
4.9 KiB
C
/*
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* Based on arch/arm/include/asm/cacheflush.h
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*
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* Copyright (C) 1999-2002 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CACHEFLUSH_H
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#define __ASM_CACHEFLUSH_H
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#include <linux/mm.h>
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/*
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* This flag is used to indicate that the page pointed to by a pte is clean
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* and does not require cleaning before returning it to the user.
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*/
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#define PG_dcache_clean PG_arch_1
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/*
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* MM Cache Management
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* ===================
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*
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* The arch/arm64/mm/cache.S implements these methods.
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*
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* Start addresses are inclusive and end addresses are exclusive; start
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* addresses should be rounded down, end addresses up.
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*
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* See Documentation/cachetlb.txt for more information. Please note that
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* the implementation assumes non-aliasing VIPT D-cache and (aliasing)
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* VIPT or ASID-tagged VIVT I-cache.
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*
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* flush_cache_mm(mm)
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*
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* Clean and invalidate all user space cache entries
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* before a change of page tables.
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*
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* flush_icache_range(start, end)
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*
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* Ensure coherency between the I-cache and the D-cache in the
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* region described by start, end.
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* - start - virtual start address
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* - end - virtual end address
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*
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* __flush_cache_user_range(start, end)
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*
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* Ensure coherency between the I-cache and the D-cache in the
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* region described by start, end.
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* - start - virtual start address
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* - end - virtual end address
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*
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* __flush_dcache_area(kaddr, size)
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*
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* Ensure that the data held in page is written back.
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* - kaddr - page address
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* - size - region size
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*/
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extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
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extern void flush_icache_range(unsigned long start, unsigned long end);
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extern void __flush_dcache_area(void *addr, size_t len);
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extern void __clean_dcache_area_poc(void *addr, size_t len);
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extern void __clean_dcache_area_pou(void *addr, size_t len);
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extern long __flush_cache_user_range(unsigned long start, unsigned long end);
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extern void sync_icache_aliases(void *kaddr, unsigned long len);
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static inline void flush_cache_mm(struct mm_struct *mm)
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{
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}
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static inline void flush_cache_page(struct vm_area_struct *vma,
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unsigned long user_addr, unsigned long pfn)
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{
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}
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/*
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* Cache maintenance functions used by the DMA API. No to be used directly.
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*/
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extern void __dma_map_area(const void *, size_t, int);
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extern void __dma_unmap_area(const void *, size_t, int);
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extern void __dma_flush_area(const void *, size_t);
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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* space" model to handle this.
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*/
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extern void copy_to_user_page(struct vm_area_struct *, struct page *,
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unsigned long, void *, const void *, unsigned long);
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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} while (0)
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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/*
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* flush_dcache_page is used when the kernel has written to the page
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* cache page at virtual address page->virtual.
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*
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* If this page isn't mapped (ie, page_mapping == NULL), or it might
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* have userspace mappings, then we _must_ always clean + invalidate
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* the dcache entries associated with the kernel mapping.
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*
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* Otherwise we can defer the operation, and clean the cache when we are
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* about to change to user space. This is the same method as used on SPARC64.
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* See update_mmu_cache for the user space part.
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*/
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *);
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static inline void __flush_icache_all(void)
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{
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asm("ic ialluis");
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dsb(ish);
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}
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#define flush_dcache_mmap_lock(mapping) \
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spin_lock_irq(&(mapping)->tree_lock)
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#define flush_dcache_mmap_unlock(mapping) \
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spin_unlock_irq(&(mapping)->tree_lock)
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/*
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* We don't appear to need to do anything here. In fact, if we did, we'd
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* duplicate cache flushing elsewhere performed by flush_dcache_page().
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*/
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#define flush_icache_page(vma,page) do { } while (0)
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/*
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* Not required on AArch64 (PIPT or VIPT non-aliasing D-cache).
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*/
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static inline void flush_cache_vmap(unsigned long start, unsigned long end)
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{
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}
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static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
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{
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}
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int set_memory_ro(unsigned long addr, int numpages);
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int set_memory_rw(unsigned long addr, int numpages);
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int set_memory_x(unsigned long addr, int numpages);
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int set_memory_nx(unsigned long addr, int numpages);
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#endif
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