![Takashi Iwai](/assets/img/avatar_default.png)
- Further work on the dmaengine helpers, including support for configuring the parameters for DMA by reading the capabilities of the DMA controller which removes some guesswork and magic numbers fromm drivers. - A refresh of the documentation. - Conversions of many drivers to direct regmap API usage in order to allow the ASoC level register I/O code to be removed, this will hopefully be completed by v3.14. - Support for using async register I/O in DAPM, reducing the time taken to implement power transitions on systems that support it. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJSajLdAAoJELSic+t+oim9MVEQAJ3t7df5K9R/OynjhKiEFxpP cBWo306CegZ5oO17UqG+SReJkOWgUI8zIUkNC818suTjtgyhv4WUBx1QgXG8akO5 arHZEQGyReLxgWbnO5ScP7BJt5ZYldfQWN+NPnNlzwvVA8R4xChvAwuHL+kUSSYW DrOb0ag/Gtn2jQo3o9GbZb5c3UhZqoMg/pQSoVtnvG/O8N/xR0yoeXGsdJv1su6g OKhCJTRWU8v3FONatR2wWXnSrCBOeJ2Ec7YUJil1FQQdENYZfV3AOsFHxmqsyG2O Xj2P7CioY0JY7dtFcKjrXgsnjvgZmVdVsdegTJPWS9RjunjyupvSyhMhZYkoA60j V7RxyIbHAx7hILQqCYYhlOczYHom4MSwAGGt7y7T3oKt0432RvIjE2fP7sTGaqD8 wzuVYuVl4km03xX9g9abF6xjyDE6e+4wun+d8kSvOosvd/nF47gkXUXEvPZh0Ley 013e5fHNDaNF4uaSVXE169JyVxVnHP6nXJDRWZakXsryGXGUpn0quIzobf6fb6XE fY5Q3QoyP5rHdSMIvGN5Gi76KsHF5CWILWqcWLEVPLnaf9gJmrp3IypmF1c8i7VE CrcTim5mhNePEX56skRaHhpYHmsxYApSAzxNAA/t3cJ2rtwb87jMM4jOcjHi/war emSVe5lXkcwv/lU/Pa0N =rVsK -----END PGP SIGNATURE----- Merge tag 'asoc-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next ASoC: Updates for v3.13 - Further work on the dmaengine helpers, including support for configuring the parameters for DMA by reading the capabilities of the DMA controller which removes some guesswork and magic numbers fromm drivers. - A refresh of the documentation. - Conversions of many drivers to direct regmap API usage in order to allow the ASoC level register I/O code to be removed, this will hopefully be completed by v3.14. - Support for using async register I/O in DAPM, reducing the time taken to implement power transitions on systems that support it.
595 lines
15 KiB
C
595 lines
15 KiB
C
/*
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* tegra30_i2s.c - Tegra30 I2S driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* Based on code copyright/by:
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*
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* Copyright (c) 2009-2010, NVIDIA Corporation.
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* Scott Peterson <speterson@nvidia.com>
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*
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* Copyright (C) 2010 Google, Inc.
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* Iliyan Malchev <malchev@google.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#include "tegra30_ahub.h"
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#include "tegra30_i2s.h"
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#define DRV_NAME "tegra30-i2s"
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static int tegra30_i2s_runtime_suspend(struct device *dev)
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{
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struct tegra30_i2s *i2s = dev_get_drvdata(dev);
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regcache_cache_only(i2s->regmap, true);
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clk_disable_unprepare(i2s->clk_i2s);
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return 0;
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}
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static int tegra30_i2s_runtime_resume(struct device *dev)
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{
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struct tegra30_i2s *i2s = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(i2s->clk_i2s);
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if (ret) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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return ret;
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}
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regcache_cache_only(i2s->regmap, false);
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return 0;
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}
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static int tegra30_i2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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int ret;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
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&i2s->playback_dma_data.addr,
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&i2s->playback_dma_data.slave_id);
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i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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i2s->playback_dma_data.maxburst = 4;
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tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
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i2s->playback_fifo_cif);
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} else {
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ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
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&i2s->capture_dma_data.addr,
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&i2s->capture_dma_data.slave_id);
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i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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i2s->capture_dma_data.maxburst = 4;
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tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
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i2s->capture_i2s_cif);
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}
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return ret;
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}
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static void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
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tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
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} else {
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tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
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tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
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}
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}
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static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
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unsigned int fmt)
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{
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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unsigned int mask, val;
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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default:
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return -EINVAL;
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}
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mask = TEGRA30_I2S_CTRL_MASTER_ENABLE;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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val = TEGRA30_I2S_CTRL_MASTER_ENABLE;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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break;
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default:
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return -EINVAL;
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}
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mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
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TEGRA30_I2S_CTRL_LRCK_MASK;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_A:
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
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val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
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break;
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case SND_SOC_DAIFMT_I2S:
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
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break;
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default:
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return -EINVAL;
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}
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pm_runtime_get_sync(dai->dev);
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
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pm_runtime_put(dai->dev);
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return 0;
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}
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static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->dev;
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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unsigned int mask, val, reg;
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int ret, sample_size, srate, i2sclock, bitcnt;
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struct tegra30_ahub_cif_conf cif_conf;
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if (params_channels(params) != 2)
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return -EINVAL;
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mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
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sample_size = 16;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
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srate = params_rate(params);
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/* Final "* 2" required by Tegra hardware */
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i2sclock = srate * params_channels(params) * sample_size * 2;
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bitcnt = (i2sclock / (2 * srate)) - 1;
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if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
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return -EINVAL;
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ret = clk_set_rate(i2s->clk_i2s, i2sclock);
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if (ret) {
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dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
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return ret;
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}
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val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
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if (i2sclock % (2 * srate))
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val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
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regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
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cif_conf.threshold = 0;
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cif_conf.audio_channels = 2;
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cif_conf.client_channels = 2;
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cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
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cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
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cif_conf.expand = 0;
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cif_conf.stereo_conv = 0;
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cif_conf.replicate = 0;
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cif_conf.truncate = 0;
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cif_conf.mono_conv = 0;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
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reg = TEGRA30_I2S_CIF_RX_CTRL;
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} else {
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cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
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reg = TEGRA30_I2S_CIF_TX_CTRL;
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}
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i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
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val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
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(1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
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regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
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return 0;
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}
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static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
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{
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tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
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TEGRA30_I2S_CTRL_XFER_EN_TX,
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TEGRA30_I2S_CTRL_XFER_EN_TX);
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}
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static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
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{
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tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
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TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
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}
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static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
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{
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tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
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TEGRA30_I2S_CTRL_XFER_EN_RX,
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TEGRA30_I2S_CTRL_XFER_EN_RX);
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}
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static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
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{
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tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
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regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
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TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
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}
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static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_RESUME:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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tegra30_i2s_start_playback(i2s);
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else
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tegra30_i2s_start_capture(i2s);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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tegra30_i2s_stop_playback(i2s);
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else
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tegra30_i2s_stop_capture(i2s);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int tegra30_i2s_probe(struct snd_soc_dai *dai)
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{
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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dai->capture_dma_data = &i2s->capture_dma_data;
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dai->playback_dma_data = &i2s->playback_dma_data;
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return 0;
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}
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static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
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.startup = tegra30_i2s_startup,
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.shutdown = tegra30_i2s_shutdown,
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.set_fmt = tegra30_i2s_set_fmt,
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.hw_params = tegra30_i2s_hw_params,
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.trigger = tegra30_i2s_trigger,
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};
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static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
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.probe = tegra30_i2s_probe,
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.playback = {
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.stream_name = "Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.capture = {
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.stream_name = "Capture",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = &tegra30_i2s_dai_ops,
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.symmetric_rates = 1,
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};
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static const struct snd_soc_component_driver tegra30_i2s_component = {
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.name = DRV_NAME,
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};
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static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA30_I2S_CTRL:
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case TEGRA30_I2S_TIMING:
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case TEGRA30_I2S_OFFSET:
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case TEGRA30_I2S_CH_CTRL:
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case TEGRA30_I2S_SLOT_CTRL:
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case TEGRA30_I2S_CIF_RX_CTRL:
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case TEGRA30_I2S_CIF_TX_CTRL:
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case TEGRA30_I2S_FLOWCTL:
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case TEGRA30_I2S_TX_STEP:
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case TEGRA30_I2S_FLOW_STATUS:
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case TEGRA30_I2S_FLOW_TOTAL:
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case TEGRA30_I2S_FLOW_OVER:
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case TEGRA30_I2S_FLOW_UNDER:
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case TEGRA30_I2S_LCOEF_1_4_0:
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case TEGRA30_I2S_LCOEF_1_4_1:
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case TEGRA30_I2S_LCOEF_1_4_2:
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case TEGRA30_I2S_LCOEF_1_4_3:
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case TEGRA30_I2S_LCOEF_1_4_4:
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case TEGRA30_I2S_LCOEF_1_4_5:
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case TEGRA30_I2S_LCOEF_2_4_0:
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case TEGRA30_I2S_LCOEF_2_4_1:
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case TEGRA30_I2S_LCOEF_2_4_2:
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return true;
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default:
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return false;
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}
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}
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static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA30_I2S_FLOW_STATUS:
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case TEGRA30_I2S_FLOW_TOTAL:
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case TEGRA30_I2S_FLOW_OVER:
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case TEGRA30_I2S_FLOW_UNDER:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config tegra30_i2s_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = TEGRA30_I2S_LCOEF_2_4_2,
|
|
.writeable_reg = tegra30_i2s_wr_rd_reg,
|
|
.readable_reg = tegra30_i2s_wr_rd_reg,
|
|
.volatile_reg = tegra30_i2s_volatile_reg,
|
|
.cache_type = REGCACHE_RBTREE,
|
|
};
|
|
|
|
static const struct tegra30_i2s_soc_data tegra30_i2s_config = {
|
|
.set_audio_cif = tegra30_ahub_set_cif,
|
|
};
|
|
|
|
static const struct tegra30_i2s_soc_data tegra124_i2s_config = {
|
|
.set_audio_cif = tegra124_ahub_set_cif,
|
|
};
|
|
|
|
static const struct of_device_id tegra30_i2s_of_match[] = {
|
|
{ .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
|
|
{ .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
|
|
{},
|
|
};
|
|
|
|
static int tegra30_i2s_platform_probe(struct platform_device *pdev)
|
|
{
|
|
struct tegra30_i2s *i2s;
|
|
const struct of_device_id *match;
|
|
u32 cif_ids[2];
|
|
struct resource *mem, *memregion;
|
|
void __iomem *regs;
|
|
int ret;
|
|
|
|
i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
|
|
if (!i2s) {
|
|
dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
dev_set_drvdata(&pdev->dev, i2s);
|
|
|
|
match = of_match_device(tegra30_i2s_of_match, &pdev->dev);
|
|
if (!match) {
|
|
dev_err(&pdev->dev, "Error: No device match found\n");
|
|
ret = -ENODEV;
|
|
goto err;
|
|
}
|
|
i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data;
|
|
|
|
i2s->dai = tegra30_i2s_dai_template;
|
|
i2s->dai.name = dev_name(&pdev->dev);
|
|
|
|
ret = of_property_read_u32_array(pdev->dev.of_node,
|
|
"nvidia,ahub-cif-ids", cif_ids,
|
|
ARRAY_SIZE(cif_ids));
|
|
if (ret < 0)
|
|
goto err;
|
|
|
|
i2s->playback_i2s_cif = cif_ids[0];
|
|
i2s->capture_i2s_cif = cif_ids[1];
|
|
|
|
i2s->clk_i2s = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(i2s->clk_i2s)) {
|
|
dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
|
|
ret = PTR_ERR(i2s->clk_i2s);
|
|
goto err;
|
|
}
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!mem) {
|
|
dev_err(&pdev->dev, "No memory resource\n");
|
|
ret = -ENODEV;
|
|
goto err_clk_put;
|
|
}
|
|
|
|
memregion = devm_request_mem_region(&pdev->dev, mem->start,
|
|
resource_size(mem), DRV_NAME);
|
|
if (!memregion) {
|
|
dev_err(&pdev->dev, "Memory region already claimed\n");
|
|
ret = -EBUSY;
|
|
goto err_clk_put;
|
|
}
|
|
|
|
regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
|
|
if (!regs) {
|
|
dev_err(&pdev->dev, "ioremap failed\n");
|
|
ret = -ENOMEM;
|
|
goto err_clk_put;
|
|
}
|
|
|
|
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
|
&tegra30_i2s_regmap_config);
|
|
if (IS_ERR(i2s->regmap)) {
|
|
dev_err(&pdev->dev, "regmap init failed\n");
|
|
ret = PTR_ERR(i2s->regmap);
|
|
goto err_clk_put;
|
|
}
|
|
regcache_cache_only(i2s->regmap, true);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
if (!pm_runtime_enabled(&pdev->dev)) {
|
|
ret = tegra30_i2s_runtime_resume(&pdev->dev);
|
|
if (ret)
|
|
goto err_pm_disable;
|
|
}
|
|
|
|
ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
|
|
&i2s->dai, 1);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
|
|
ret = -ENOMEM;
|
|
goto err_suspend;
|
|
}
|
|
|
|
ret = tegra_pcm_platform_register(&pdev->dev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
|
|
goto err_unregister_component;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_unregister_component:
|
|
snd_soc_unregister_component(&pdev->dev);
|
|
err_suspend:
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra30_i2s_runtime_suspend(&pdev->dev);
|
|
err_pm_disable:
|
|
pm_runtime_disable(&pdev->dev);
|
|
err_clk_put:
|
|
clk_put(i2s->clk_i2s);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static int tegra30_i2s_platform_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra30_i2s_runtime_suspend(&pdev->dev);
|
|
|
|
tegra_pcm_platform_unregister(&pdev->dev);
|
|
snd_soc_unregister_component(&pdev->dev);
|
|
|
|
clk_put(i2s->clk_i2s);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int tegra30_i2s_suspend(struct device *dev)
|
|
{
|
|
struct tegra30_i2s *i2s = dev_get_drvdata(dev);
|
|
|
|
regcache_mark_dirty(i2s->regmap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra30_i2s_resume(struct device *dev)
|
|
{
|
|
struct tegra30_i2s *i2s = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = pm_runtime_get_sync(dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = regcache_sync(i2s->regmap);
|
|
pm_runtime_put(dev);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops tegra30_i2s_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
|
|
tegra30_i2s_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra30_i2s_suspend, tegra30_i2s_resume)
|
|
};
|
|
|
|
static struct platform_driver tegra30_i2s_driver = {
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = tegra30_i2s_of_match,
|
|
.pm = &tegra30_i2s_pm_ops,
|
|
},
|
|
.probe = tegra30_i2s_platform_probe,
|
|
.remove = tegra30_i2s_platform_remove,
|
|
};
|
|
module_platform_driver(tegra30_i2s_driver);
|
|
|
|
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
|