1727339590
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
158 lines
3.2 KiB
C
158 lines
3.2 KiB
C
/*
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* H8S TPU Driver
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*
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* Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
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*
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clocksource.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define TCR 0x0
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#define TSR 0x5
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#define TCNT 0x6
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#define TCFV 0x10
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struct tpu_priv {
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struct clocksource cs;
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void __iomem *mapbase1;
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void __iomem *mapbase2;
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raw_spinlock_t lock;
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unsigned int cs_enabled;
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};
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static inline unsigned long read_tcnt32(struct tpu_priv *p)
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{
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unsigned long tcnt;
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tcnt = ioread16be(p->mapbase1 + TCNT) << 16;
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tcnt |= ioread16be(p->mapbase2 + TCNT);
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return tcnt;
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}
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static int tpu_get_counter(struct tpu_priv *p, unsigned long long *val)
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{
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unsigned long v1, v2, v3;
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int o1, o2;
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o1 = ioread8(p->mapbase1 + TSR) & TCFV;
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/* Make sure the timer value is stable. Stolen from acpi_pm.c */
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do {
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o2 = o1;
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v1 = read_tcnt32(p);
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v2 = read_tcnt32(p);
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v3 = read_tcnt32(p);
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o1 = ioread8(p->mapbase1 + TSR) & TCFV;
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} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
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|| (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
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*val = v2;
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return o1;
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}
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static inline struct tpu_priv *cs_to_priv(struct clocksource *cs)
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{
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return container_of(cs, struct tpu_priv, cs);
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}
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static u64 tpu_clocksource_read(struct clocksource *cs)
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{
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struct tpu_priv *p = cs_to_priv(cs);
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unsigned long flags;
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unsigned long long value;
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raw_spin_lock_irqsave(&p->lock, flags);
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if (tpu_get_counter(p, &value))
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value += 0x100000000;
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raw_spin_unlock_irqrestore(&p->lock, flags);
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return value;
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}
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static int tpu_clocksource_enable(struct clocksource *cs)
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{
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struct tpu_priv *p = cs_to_priv(cs);
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WARN_ON(p->cs_enabled);
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iowrite16be(0, p->mapbase1 + TCNT);
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iowrite16be(0, p->mapbase2 + TCNT);
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iowrite8(0x0f, p->mapbase1 + TCR);
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iowrite8(0x03, p->mapbase2 + TCR);
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p->cs_enabled = true;
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return 0;
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}
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static void tpu_clocksource_disable(struct clocksource *cs)
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{
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struct tpu_priv *p = cs_to_priv(cs);
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WARN_ON(!p->cs_enabled);
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iowrite8(0, p->mapbase1 + TCR);
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iowrite8(0, p->mapbase2 + TCR);
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p->cs_enabled = false;
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}
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static struct tpu_priv tpu_priv = {
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.cs = {
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.name = "H8S_TPU",
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.rating = 200,
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.read = tpu_clocksource_read,
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.enable = tpu_clocksource_enable,
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.disable = tpu_clocksource_disable,
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.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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},
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};
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#define CH_L 0
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#define CH_H 1
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static int __init h8300_tpu_init(struct device_node *node)
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{
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void __iomem *base[2];
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struct clk *clk;
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int ret = -ENXIO;
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("failed to get clock for clocksource\n");
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return PTR_ERR(clk);
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}
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base[CH_L] = of_iomap(node, CH_L);
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if (!base[CH_L]) {
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pr_err("failed to map registers for clocksource\n");
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goto free_clk;
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}
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base[CH_H] = of_iomap(node, CH_H);
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if (!base[CH_H]) {
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pr_err("failed to map registers for clocksource\n");
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goto unmap_L;
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}
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tpu_priv.mapbase1 = base[CH_L];
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tpu_priv.mapbase2 = base[CH_H];
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return clocksource_register_hz(&tpu_priv.cs, clk_get_rate(clk) / 64);
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unmap_L:
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iounmap(base[CH_H]);
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free_clk:
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clk_put(clk);
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return ret;
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}
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TIMER_OF_DECLARE(h8300_tpu, "renesas,tpu", h8300_tpu_init);
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