![Thomas Gleixner](/assets/img/avatar_default.png)
No functional change. Just convert to the new interface. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Grant Likely <grant.likely@linaro.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Acked-by: Chris Metcalf <cmetcalf@tilera.com> Link: http://lkml.kernel.org/r/20140507154338.132662495@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
1611 lines
43 KiB
C
1611 lines
43 KiB
C
/*
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* Copyright 2012 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/kernel.h>
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#include <linux/mmzone.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/capability.h>
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#include <linux/sched.h>
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#include <linux/errno.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <linux/ctype.h>
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#include <asm/processor.h>
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#include <asm/sections.h>
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#include <asm/byteorder.h>
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#include <gxio/iorpc_globals.h>
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#include <gxio/kiorpc.h>
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#include <gxio/trio.h>
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#include <gxio/iorpc_trio.h>
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#include <hv/drv_trio_intf.h>
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#include <arch/sim.h>
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/*
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* This file containes the routines to search for PCI buses,
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* enumerate the buses, and configure any attached devices.
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*/
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#define DEBUG_PCI_CFG 0
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#if DEBUG_PCI_CFG
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#define TRACE_CFG_WR(size, val, bus, dev, func, offset) \
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pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
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size, val, bus, dev, func, offset & 0xFFF);
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#define TRACE_CFG_RD(size, val, bus, dev, func, offset) \
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pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \
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size, val, bus, dev, func, offset & 0xFFF);
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#else
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#define TRACE_CFG_WR(...)
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#define TRACE_CFG_RD(...)
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#endif
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static int pci_probe = 1;
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/* Information on the PCIe RC ports configuration. */
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static int pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
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/*
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* On some platforms with one or more Gx endpoint ports, we need to
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* delay the PCIe RC port probe for a few seconds to work around
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* a HW PCIe link-training bug. The exact delay is specified with
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* a kernel boot argument in the form of "pcie_rc_delay=T,P,S",
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* where T is the TRIO instance number, P is the port number and S is
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* the delay in seconds. If the argument is specified, but the delay is
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* not provided, the value will be DEFAULT_RC_DELAY.
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*/
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static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
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/* Default number of seconds that the PCIe RC port probe can be delayed. */
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#define DEFAULT_RC_DELAY 10
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/* The PCI I/O space size in each PCI domain. */
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#define IO_SPACE_SIZE 0x10000
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/* Provide shorter versions of some very long constant names. */
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#define AUTO_CONFIG_RC \
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TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC
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#define AUTO_CONFIG_RC_G1 \
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TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1
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#define AUTO_CONFIG_EP \
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TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT
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#define AUTO_CONFIG_EP_G1 \
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TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1
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/* Array of the PCIe ports configuration info obtained from the BIB. */
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struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO];
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/* Number of configured TRIO instances. */
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int num_trio_shims;
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/* All drivers share the TRIO contexts defined here. */
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gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
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/* Pointer to an array of PCIe RC controllers. */
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struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
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int num_rc_controllers;
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static struct pci_ops tile_cfg_ops;
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/* Mask of CPUs that should receive PCIe interrupts. */
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static struct cpumask intr_cpus_map;
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/* We don't need to worry about the alignment of resources. */
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size,
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resource_size_t align)
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{
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return res->start;
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}
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EXPORT_SYMBOL(pcibios_align_resource);
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/*
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* Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
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* For now, we simply send interrupts to non-dataplane CPUs.
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* We may implement methods to allow user to specify the target CPUs,
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* e.g. via boot arguments.
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*/
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static int tile_irq_cpu(int irq)
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{
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unsigned int count;
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int i = 0;
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int cpu;
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count = cpumask_weight(&intr_cpus_map);
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if (unlikely(count == 0)) {
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pr_warning("intr_cpus_map empty, interrupts will be"
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" delievered to dataplane tiles\n");
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return irq % (smp_height * smp_width);
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}
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count = irq % count;
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for_each_cpu(cpu, &intr_cpus_map) {
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if (i++ == count)
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break;
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}
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return cpu;
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}
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/* Open a file descriptor to the TRIO shim. */
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static int tile_pcie_open(int trio_index)
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{
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gxio_trio_context_t *context = &trio_contexts[trio_index];
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int ret;
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int mac;
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/* This opens a file descriptor to the TRIO shim. */
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ret = gxio_trio_init(context, trio_index);
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if (ret < 0)
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goto gxio_trio_init_failure;
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/* Allocate an ASID for the kernel. */
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ret = gxio_trio_alloc_asids(context, 1, 0, 0);
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if (ret < 0) {
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pr_err("PCI: ASID alloc failure on TRIO %d, give up\n",
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trio_index);
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goto asid_alloc_failure;
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}
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context->asid = ret;
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#ifdef USE_SHARED_PCIE_CONFIG_REGION
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/*
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* Alloc a PIO region for config access, shared by all MACs per TRIO.
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* This shouldn't fail since the kernel is supposed to the first
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* client of the TRIO's PIO regions.
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*/
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ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0);
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if (ret < 0) {
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pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n",
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trio_index);
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goto pio_alloc_failure;
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}
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context->pio_cfg_index = ret;
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/*
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* For PIO CFG, the bus_address_hi parameter is 0. The mac parameter
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* is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR.
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*/
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ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index,
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0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
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if (ret < 0) {
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pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n",
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trio_index);
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goto pio_alloc_failure;
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}
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#endif
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/* Get the properties of the PCIe ports on this TRIO instance. */
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ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]);
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if (ret < 0) {
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pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d,"
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" on TRIO %d\n", ret, trio_index);
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goto get_port_property_failure;
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}
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context->mmio_base_mac =
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iorpc_ioremap(context->fd, 0, HV_TRIO_CONFIG_IOREMAP_SIZE);
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if (context->mmio_base_mac == NULL) {
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pr_err("PCI: TRIO config space mapping failure, error %d,"
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" on TRIO %d\n", ret, trio_index);
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ret = -ENOMEM;
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goto trio_mmio_mapping_failure;
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}
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/* Check the port strap state which will override the BIB setting. */
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for (mac = 0; mac < TILEGX_TRIO_PCIES; mac++) {
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TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
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unsigned int reg_offset;
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/* Ignore ports that are not specified in the BIB. */
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if (!pcie_ports[trio_index].ports[mac].allow_rc &&
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!pcie_ports[trio_index].ports[mac].allow_ep)
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continue;
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reg_offset =
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(TRIO_PCIE_INTFC_PORT_CONFIG <<
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TRIO_CFG_REGION_ADDR__REG_SHIFT) |
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(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
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TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
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(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
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port_config.word =
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__gxio_mmio_read(context->mmio_base_mac + reg_offset);
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if (port_config.strap_state != AUTO_CONFIG_RC &&
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port_config.strap_state != AUTO_CONFIG_RC_G1) {
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/*
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* If this is really intended to be an EP port, record
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* it so that the endpoint driver will know about it.
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*/
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if (port_config.strap_state == AUTO_CONFIG_EP ||
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port_config.strap_state == AUTO_CONFIG_EP_G1)
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pcie_ports[trio_index].ports[mac].allow_ep = 1;
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}
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}
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return ret;
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trio_mmio_mapping_failure:
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get_port_property_failure:
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asid_alloc_failure:
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#ifdef USE_SHARED_PCIE_CONFIG_REGION
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pio_alloc_failure:
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#endif
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hv_dev_close(context->fd);
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gxio_trio_init_failure:
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context->fd = -1;
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return ret;
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}
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static int __init tile_trio_init(void)
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{
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int i;
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/* We loop over all the TRIO shims. */
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for (i = 0; i < TILEGX_NUM_TRIO; i++) {
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if (tile_pcie_open(i) < 0)
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continue;
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num_trio_shims++;
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}
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return 0;
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}
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postcore_initcall(tile_trio_init);
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static void tilegx_legacy_irq_ack(struct irq_data *d)
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{
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__insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
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}
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static void tilegx_legacy_irq_mask(struct irq_data *d)
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{
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__insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
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}
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static void tilegx_legacy_irq_unmask(struct irq_data *d)
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{
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__insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
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}
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static struct irq_chip tilegx_legacy_irq_chip = {
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.name = "tilegx_legacy_irq",
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.irq_ack = tilegx_legacy_irq_ack,
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.irq_mask = tilegx_legacy_irq_mask,
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.irq_unmask = tilegx_legacy_irq_unmask,
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/* TBD: support set_affinity. */
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};
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/*
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* This is a wrapper function of the kernel level-trigger interrupt
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* handler handle_level_irq() for PCI legacy interrupts. The TRIO
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* is configured such that only INTx Assert interrupts are proxied
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* to Linux which just calls handle_level_irq() after clearing the
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* MAC INTx Assert status bit associated with this interrupt.
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*/
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static void trio_handle_level_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct pci_controller *controller = irq_desc_get_handler_data(desc);
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gxio_trio_context_t *trio_context = controller->trio;
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uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
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int mac = controller->mac;
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unsigned int reg_offset;
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uint64_t level_mask;
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handle_level_irq(irq, desc);
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/*
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* Clear the INTx Level status, otherwise future interrupts are
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* not sent.
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*/
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reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS <<
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TRIO_CFG_REGION_ADDR__REG_SHIFT) |
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(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
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TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
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(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
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level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx;
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__gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask);
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}
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/*
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* Create kernel irqs and set up the handlers for the legacy interrupts.
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* Also some minimum initialization for the MSI support.
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*/
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static int tile_init_irqs(struct pci_controller *controller)
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{
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int i;
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int j;
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int irq;
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int result;
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cpumask_copy(&intr_cpus_map, cpu_online_mask);
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for (i = 0; i < 4; i++) {
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gxio_trio_context_t *context = controller->trio;
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int cpu;
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/* Ask the kernel to allocate an IRQ. */
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irq = irq_alloc_hwirq(-1);
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if (!irq) {
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pr_err("PCI: no free irq vectors, failed for %d\n", i);
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goto free_irqs;
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}
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controller->irq_intx_table[i] = irq;
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/* Distribute the 4 IRQs to different tiles. */
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cpu = tile_irq_cpu(irq);
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/* Configure the TRIO intr binding for this IRQ. */
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result = gxio_trio_config_legacy_intr(context, cpu_x(cpu),
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cpu_y(cpu), KERNEL_PL,
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irq, controller->mac, i);
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if (result < 0) {
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pr_err("PCI: MAC intx config failed for %d\n", i);
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goto free_irqs;
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}
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/* Register the IRQ handler with the kernel. */
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irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip,
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trio_handle_level_irq);
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irq_set_chip_data(irq, (void *)(uint64_t)i);
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irq_set_handler_data(irq, controller);
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}
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return 0;
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free_irqs:
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for (j = 0; j < i; j++)
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irq_free_hwirq(controller->irq_intx_table[j]);
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return -1;
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}
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/*
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* Return 1 if the port is strapped to operate in RC mode.
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*/
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static int
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strapped_for_rc(gxio_trio_context_t *trio_context, int mac)
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{
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TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
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unsigned int reg_offset;
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/* Check the port configuration. */
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reg_offset =
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(TRIO_PCIE_INTFC_PORT_CONFIG <<
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TRIO_CFG_REGION_ADDR__REG_SHIFT) |
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(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
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TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
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(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
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port_config.word =
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__gxio_mmio_read(trio_context->mmio_base_mac + reg_offset);
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if (port_config.strap_state == AUTO_CONFIG_RC ||
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port_config.strap_state == AUTO_CONFIG_RC_G1)
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return 1;
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else
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return 0;
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}
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|
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/*
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* Find valid controllers and fill in pci_controller structs for each
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* of them.
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*
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* Return the number of controllers discovered.
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*/
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int __init tile_pci_init(void)
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{
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int ctl_index = 0;
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int i, j;
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if (!pci_probe) {
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pr_info("PCI: disabled by boot argument\n");
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return 0;
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}
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pr_info("PCI: Searching for controllers...\n");
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if (num_trio_shims == 0 || sim_is_simulator())
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return 0;
|
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|
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/*
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* Now determine which PCIe ports are configured to operate in RC
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* mode. There is a differece in the port configuration capability
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* between the Gx36 and Gx72 devices.
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*
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* The Gx36 has configuration capability for each of the 3 PCIe
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* interfaces (disable, auto endpoint, auto RC, etc.).
|
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* On the Gx72, you can only select one of the 3 PCIe interfaces per
|
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* TRIO to train automatically. Further, the allowable training modes
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* are reduced to four options (auto endpoint, auto RC, stream x1,
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* stream x4).
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*
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* For Gx36 ports, it must be allowed to be in RC mode by the
|
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* Board Information Block, and the hardware strapping pins must be
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* set to RC mode.
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*
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* For Gx72 ports, the port will operate in RC mode if either of the
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* following is true:
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* 1. It is allowed to be in RC mode by the Board Information Block,
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* and the BIB doesn't allow the EP mode.
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* 2. It is allowed to be in either the RC or the EP mode by the BIB,
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* and the hardware strapping pin is set to RC mode.
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*/
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for (i = 0; i < TILEGX_NUM_TRIO; i++) {
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gxio_trio_context_t *context = &trio_contexts[i];
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if (context->fd < 0)
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continue;
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for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
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int is_rc = 0;
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if (pcie_ports[i].is_gx72 &&
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pcie_ports[i].ports[j].allow_rc) {
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if (!pcie_ports[i].ports[j].allow_ep ||
|
|
strapped_for_rc(context, j))
|
|
is_rc = 1;
|
|
} else if (pcie_ports[i].ports[j].allow_rc &&
|
|
strapped_for_rc(context, j)) {
|
|
is_rc = 1;
|
|
}
|
|
if (is_rc) {
|
|
pcie_rc[i][j] = 1;
|
|
num_rc_controllers++;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return if no PCIe ports are configured to operate in RC mode. */
|
|
if (num_rc_controllers == 0)
|
|
return 0;
|
|
|
|
/* Set the TRIO pointer and MAC index for each PCIe RC port. */
|
|
for (i = 0; i < TILEGX_NUM_TRIO; i++) {
|
|
for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
|
|
if (pcie_rc[i][j]) {
|
|
pci_controllers[ctl_index].trio =
|
|
&trio_contexts[i];
|
|
pci_controllers[ctl_index].mac = j;
|
|
pci_controllers[ctl_index].trio_index = i;
|
|
ctl_index++;
|
|
if (ctl_index == num_rc_controllers)
|
|
goto out;
|
|
}
|
|
}
|
|
}
|
|
|
|
out:
|
|
/* Configure each PCIe RC port. */
|
|
for (i = 0; i < num_rc_controllers; i++) {
|
|
|
|
/* Configure the PCIe MAC to run in RC mode. */
|
|
struct pci_controller *controller = &pci_controllers[i];
|
|
|
|
controller->index = i;
|
|
controller->ops = &tile_cfg_ops;
|
|
|
|
controller->io_space.start = PCIBIOS_MIN_IO +
|
|
(i * IO_SPACE_SIZE);
|
|
controller->io_space.end = controller->io_space.start +
|
|
IO_SPACE_SIZE - 1;
|
|
BUG_ON(controller->io_space.end > IO_SPACE_LIMIT);
|
|
controller->io_space.flags = IORESOURCE_IO;
|
|
snprintf(controller->io_space_name,
|
|
sizeof(controller->io_space_name),
|
|
"PCI I/O domain %d", i);
|
|
controller->io_space.name = controller->io_space_name;
|
|
|
|
/*
|
|
* The PCI memory resource is located above the PA space.
|
|
* For every host bridge, the BAR window or the MMIO aperture
|
|
* is in range [3GB, 4GB - 1] of a 4GB space beyond the
|
|
* PA space.
|
|
*/
|
|
controller->mem_offset = TILE_PCI_MEM_START +
|
|
(i * TILE_PCI_BAR_WINDOW_TOP);
|
|
controller->mem_space.start = controller->mem_offset +
|
|
TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE;
|
|
controller->mem_space.end = controller->mem_offset +
|
|
TILE_PCI_BAR_WINDOW_TOP - 1;
|
|
controller->mem_space.flags = IORESOURCE_MEM;
|
|
snprintf(controller->mem_space_name,
|
|
sizeof(controller->mem_space_name),
|
|
"PCI mem domain %d", i);
|
|
controller->mem_space.name = controller->mem_space_name;
|
|
}
|
|
|
|
return num_rc_controllers;
|
|
}
|
|
|
|
/*
|
|
* (pin - 1) converts from the PCI standard's [1:4] convention to
|
|
* a normal [0:3] range.
|
|
*/
|
|
static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin)
|
|
{
|
|
struct pci_controller *controller =
|
|
(struct pci_controller *)dev->sysdata;
|
|
return controller->irq_intx_table[pin - 1];
|
|
}
|
|
|
|
static void fixup_read_and_payload_sizes(struct pci_controller *controller)
|
|
{
|
|
gxio_trio_context_t *trio_context = controller->trio;
|
|
struct pci_bus *root_bus = controller->root_bus;
|
|
TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control;
|
|
TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap;
|
|
unsigned int reg_offset;
|
|
struct pci_bus *child;
|
|
int mac;
|
|
int err;
|
|
|
|
mac = controller->mac;
|
|
|
|
/* Set our max read request size to be 4KB. */
|
|
reg_offset =
|
|
(TRIO_PCIE_RC_DEVICE_CONTROL <<
|
|
TRIO_CFG_REGION_ADDR__REG_SHIFT) |
|
|
(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
|
|
TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
|
|
(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
|
|
|
|
dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
|
|
reg_offset);
|
|
dev_control.max_read_req_sz = 5;
|
|
__gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
|
|
dev_control.word);
|
|
|
|
/*
|
|
* Set the max payload size supported by this Gx PCIe MAC.
|
|
* Though Gx PCIe supports Max Payload Size of up to 1024 bytes,
|
|
* experiments have shown that setting MPS to 256 yields the
|
|
* best performance.
|
|
*/
|
|
reg_offset =
|
|
(TRIO_PCIE_RC_DEVICE_CAP <<
|
|
TRIO_CFG_REGION_ADDR__REG_SHIFT) |
|
|
(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
|
|
TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
|
|
(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
|
|
|
|
rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
|
|
reg_offset);
|
|
rc_dev_cap.mps_sup = 1;
|
|
__gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
|
|
rc_dev_cap.word);
|
|
|
|
/* Configure PCI Express MPS setting. */
|
|
list_for_each_entry(child, &root_bus->children, node)
|
|
pcie_bus_configure_settings(child);
|
|
|
|
/*
|
|
* Set the mac_config register in trio based on the MPS/MRS of the link.
|
|
*/
|
|
reg_offset =
|
|
(TRIO_PCIE_RC_DEVICE_CONTROL <<
|
|
TRIO_CFG_REGION_ADDR__REG_SHIFT) |
|
|
(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
|
|
TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
|
|
(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
|
|
|
|
dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
|
|
reg_offset);
|
|
|
|
err = gxio_trio_set_mps_mrs(trio_context,
|
|
dev_control.max_payload_size,
|
|
dev_control.max_read_req_sz,
|
|
mac);
|
|
if (err < 0) {
|
|
pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, "
|
|
"MAC %d on TRIO %d\n",
|
|
mac, controller->trio_index);
|
|
}
|
|
}
|
|
|
|
static int setup_pcie_rc_delay(char *str)
|
|
{
|
|
unsigned long delay = 0;
|
|
unsigned long trio_index;
|
|
unsigned long mac;
|
|
|
|
if (str == NULL || !isdigit(*str))
|
|
return -EINVAL;
|
|
trio_index = simple_strtoul(str, (char **)&str, 10);
|
|
if (trio_index >= TILEGX_NUM_TRIO)
|
|
return -EINVAL;
|
|
|
|
if (*str != ',')
|
|
return -EINVAL;
|
|
|
|
str++;
|
|
if (!isdigit(*str))
|
|
return -EINVAL;
|
|
mac = simple_strtoul(str, (char **)&str, 10);
|
|
if (mac >= TILEGX_TRIO_PCIES)
|
|
return -EINVAL;
|
|
|
|
if (*str != '\0') {
|
|
if (*str != ',')
|
|
return -EINVAL;
|
|
|
|
str++;
|
|
if (!isdigit(*str))
|
|
return -EINVAL;
|
|
delay = simple_strtoul(str, (char **)&str, 10);
|
|
}
|
|
|
|
rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY;
|
|
return 0;
|
|
}
|
|
early_param("pcie_rc_delay", setup_pcie_rc_delay);
|
|
|
|
/* PCI initialization entry point, called by subsys_initcall. */
|
|
int __init pcibios_init(void)
|
|
{
|
|
resource_size_t offset;
|
|
LIST_HEAD(resources);
|
|
int next_busno;
|
|
int i;
|
|
|
|
tile_pci_init();
|
|
|
|
if (num_rc_controllers == 0)
|
|
return 0;
|
|
|
|
/*
|
|
* Delay a bit in case devices aren't ready. Some devices are
|
|
* known to require at least 20ms here, but we use a more
|
|
* conservative value.
|
|
*/
|
|
msleep(250);
|
|
|
|
/* Scan all of the recorded PCI controllers. */
|
|
for (next_busno = 0, i = 0; i < num_rc_controllers; i++) {
|
|
struct pci_controller *controller = &pci_controllers[i];
|
|
gxio_trio_context_t *trio_context = controller->trio;
|
|
TRIO_PCIE_INTFC_PORT_STATUS_t port_status;
|
|
TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl;
|
|
struct pci_bus *bus;
|
|
unsigned int reg_offset;
|
|
unsigned int class_code_revision;
|
|
int trio_index;
|
|
int mac;
|
|
int ret;
|
|
|
|
if (trio_context->fd < 0)
|
|
continue;
|
|
|
|
trio_index = controller->trio_index;
|
|
mac = controller->mac;
|
|
|
|
/*
|
|
* Check for PCIe link-up status to decide if we need
|
|
* to force the link to come up.
|
|
*/
|
|
reg_offset =
|
|
(TRIO_PCIE_INTFC_PORT_STATUS <<
|
|
TRIO_CFG_REGION_ADDR__REG_SHIFT) |
|
|
(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
|
|
TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
|
|
(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
|
|
|
|
port_status.word =
|
|
__gxio_mmio_read(trio_context->mmio_base_mac +
|
|
reg_offset);
|
|
if (!port_status.dl_up) {
|
|
if (rc_delay[trio_index][mac]) {
|
|
pr_info("Delaying PCIe RC TRIO init %d sec"
|
|
" on MAC %d on TRIO %d\n",
|
|
rc_delay[trio_index][mac], mac,
|
|
trio_index);
|
|
msleep(rc_delay[trio_index][mac] * 1000);
|
|
}
|
|
ret = gxio_trio_force_rc_link_up(trio_context, mac);
|
|
if (ret < 0)
|
|
pr_err("PCI: PCIE_FORCE_LINK_UP failure, "
|
|
"MAC %d on TRIO %d\n", mac, trio_index);
|
|
}
|
|
|
|
pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n", i,
|
|
trio_index, controller->mac);
|
|
|
|
/* Delay the bus probe if needed. */
|
|
if (rc_delay[trio_index][mac]) {
|
|
pr_info("Delaying PCIe RC bus enumerating %d sec"
|
|
" on MAC %d on TRIO %d\n",
|
|
rc_delay[trio_index][mac], mac,
|
|
trio_index);
|
|
msleep(rc_delay[trio_index][mac] * 1000);
|
|
} else {
|
|
/*
|
|
* Wait a bit here because some EP devices
|
|
* take longer to come up.
|
|
*/
|
|
msleep(1000);
|
|
}
|
|
|
|
/* Check for PCIe link-up status again. */
|
|
port_status.word =
|
|
__gxio_mmio_read(trio_context->mmio_base_mac +
|
|
reg_offset);
|
|
if (!port_status.dl_up) {
|
|
if (pcie_ports[trio_index].ports[mac].removable) {
|
|
pr_info("PCI: link is down, MAC %d on TRIO %d\n",
|
|
mac, trio_index);
|
|
pr_info("This is expected if no PCIe card"
|
|
" is connected to this link\n");
|
|
} else
|
|
pr_err("PCI: link is down, MAC %d on TRIO %d\n",
|
|
mac, trio_index);
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* Ensure that the link can come out of L1 power down state.
|
|
* Strictly speaking, this is needed only in the case of
|
|
* heavy RC-initiated DMAs.
|
|
*/
|
|
reg_offset =
|
|
(TRIO_PCIE_INTFC_TX_FIFO_CTL <<
|
|
TRIO_CFG_REGION_ADDR__REG_SHIFT) |
|
|
(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
|
|
TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
|
|
(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
|
|
tx_fifo_ctl.word =
|
|
__gxio_mmio_read(trio_context->mmio_base_mac +
|
|
reg_offset);
|
|
tx_fifo_ctl.min_p_credits = 0;
|
|
__gxio_mmio_write(trio_context->mmio_base_mac + reg_offset,
|
|
tx_fifo_ctl.word);
|
|
|
|
/*
|
|
* Change the device ID so that Linux bus crawl doesn't confuse
|
|
* the internal bridge with any Tilera endpoints.
|
|
*/
|
|
reg_offset =
|
|
(TRIO_PCIE_RC_DEVICE_ID_VEN_ID <<
|
|
TRIO_CFG_REGION_ADDR__REG_SHIFT) |
|
|
(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
|
|
TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
|
|
(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
|
|
|
|
__gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
|
|
(TILERA_GX36_RC_DEV_ID <<
|
|
TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) |
|
|
TILERA_VENDOR_ID);
|
|
|
|
/* Set the internal P2P bridge class code. */
|
|
reg_offset =
|
|
(TRIO_PCIE_RC_REVISION_ID <<
|
|
TRIO_CFG_REGION_ADDR__REG_SHIFT) |
|
|
(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
|
|
TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
|
|
(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
|
|
|
|
class_code_revision =
|
|
__gxio_mmio_read32(trio_context->mmio_base_mac +
|
|
reg_offset);
|
|
class_code_revision = (class_code_revision & 0xff) |
|
|
(PCI_CLASS_BRIDGE_PCI << 16);
|
|
|
|
__gxio_mmio_write32(trio_context->mmio_base_mac +
|
|
reg_offset, class_code_revision);
|
|
|
|
#ifdef USE_SHARED_PCIE_CONFIG_REGION
|
|
|
|
/* Map in the MMIO space for the PIO region. */
|
|
offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) |
|
|
(((unsigned long long)mac) <<
|
|
TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
|
|
|
|
#else
|
|
|
|
/* Alloc a PIO region for PCI config access per MAC. */
|
|
ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
|
|
if (ret < 0) {
|
|
pr_err("PCI: PCI CFG PIO alloc failure for mac %d "
|
|
"on TRIO %d, give up\n", mac, trio_index);
|
|
|
|
continue;
|
|
}
|
|
|
|
trio_context->pio_cfg_index[mac] = ret;
|
|
|
|
/* For PIO CFG, the bus_address_hi parameter is 0. */
|
|
ret = gxio_trio_init_pio_region_aux(trio_context,
|
|
trio_context->pio_cfg_index[mac],
|
|
mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
|
|
if (ret < 0) {
|
|
pr_err("PCI: PCI CFG PIO init failure for mac %d "
|
|
"on TRIO %d, give up\n", mac, trio_index);
|
|
|
|
continue;
|
|
}
|
|
|
|
offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) |
|
|
(((unsigned long long)mac) <<
|
|
TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
|
|
|
|
#endif
|
|
|
|
/*
|
|
* To save VMALLOC space, we take advantage of the fact that
|
|
* bit 29 in the PIO CFG address format is reserved 0. With
|
|
* TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT being 30,
|
|
* this cuts VMALLOC space usage from 1GB to 512MB per mac.
|
|
*/
|
|
trio_context->mmio_base_pio_cfg[mac] =
|
|
iorpc_ioremap(trio_context->fd, offset, (1UL <<
|
|
(TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT - 1)));
|
|
if (trio_context->mmio_base_pio_cfg[mac] == NULL) {
|
|
pr_err("PCI: PIO map failure for mac %d on TRIO %d\n",
|
|
mac, trio_index);
|
|
|
|
continue;
|
|
}
|
|
|
|
/* Initialize the PCIe interrupts. */
|
|
if (tile_init_irqs(controller)) {
|
|
pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n",
|
|
mac, trio_index);
|
|
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* The PCI memory resource is located above the PA space.
|
|
* The memory range for the PCI root bus should not overlap
|
|
* with the physical RAM.
|
|
*/
|
|
pci_add_resource_offset(&resources, &controller->mem_space,
|
|
controller->mem_offset);
|
|
pci_add_resource(&resources, &controller->io_space);
|
|
controller->first_busno = next_busno;
|
|
bus = pci_scan_root_bus(NULL, next_busno, controller->ops,
|
|
controller, &resources);
|
|
controller->root_bus = bus;
|
|
next_busno = bus->busn_res.end + 1;
|
|
}
|
|
|
|
/* Do machine dependent PCI interrupt routing */
|
|
pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
|
|
|
|
/*
|
|
* This comes from the generic Linux PCI driver.
|
|
*
|
|
* It allocates all of the resources (I/O memory, etc)
|
|
* associated with the devices read in above.
|
|
*/
|
|
pci_assign_unassigned_resources();
|
|
|
|
/* Record the I/O resources in the PCI controller structure. */
|
|
for (i = 0; i < num_rc_controllers; i++) {
|
|
struct pci_controller *controller = &pci_controllers[i];
|
|
gxio_trio_context_t *trio_context = controller->trio;
|
|
struct pci_bus *root_bus = pci_controllers[i].root_bus;
|
|
int ret;
|
|
int j;
|
|
|
|
/*
|
|
* Skip controllers that are not properly initialized or
|
|
* have down links.
|
|
*/
|
|
if (root_bus == NULL)
|
|
continue;
|
|
|
|
/* Configure the max_payload_size values for this domain. */
|
|
fixup_read_and_payload_sizes(controller);
|
|
|
|
/* Alloc a PIO region for PCI memory access for each RC port. */
|
|
ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
|
|
if (ret < 0) {
|
|
pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, "
|
|
"give up\n", controller->trio_index,
|
|
controller->mac);
|
|
|
|
continue;
|
|
}
|
|
|
|
controller->pio_mem_index = ret;
|
|
|
|
/*
|
|
* For PIO MEM, the bus_address_hi parameter is hard-coded 0
|
|
* because we always assign 32-bit PCI bus BAR ranges.
|
|
*/
|
|
ret = gxio_trio_init_pio_region_aux(trio_context,
|
|
controller->pio_mem_index,
|
|
controller->mac,
|
|
0,
|
|
0);
|
|
if (ret < 0) {
|
|
pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, "
|
|
"give up\n", controller->trio_index,
|
|
controller->mac);
|
|
|
|
continue;
|
|
}
|
|
|
|
#ifdef CONFIG_TILE_PCI_IO
|
|
/*
|
|
* Alloc a PIO region for PCI I/O space access for each RC port.
|
|
*/
|
|
ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
|
|
if (ret < 0) {
|
|
pr_err("PCI: I/O PIO alloc failure on TRIO %d mac %d, "
|
|
"give up\n", controller->trio_index,
|
|
controller->mac);
|
|
|
|
continue;
|
|
}
|
|
|
|
controller->pio_io_index = ret;
|
|
|
|
/*
|
|
* For PIO IO, the bus_address_hi parameter is hard-coded 0
|
|
* because PCI I/O address space is 32-bit.
|
|
*/
|
|
ret = gxio_trio_init_pio_region_aux(trio_context,
|
|
controller->pio_io_index,
|
|
controller->mac,
|
|
0,
|
|
HV_TRIO_PIO_FLAG_IO_SPACE);
|
|
if (ret < 0) {
|
|
pr_err("PCI: I/O PIO init failure on TRIO %d mac %d, "
|
|
"give up\n", controller->trio_index,
|
|
controller->mac);
|
|
|
|
continue;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Configure a Mem-Map region for each memory controller so
|
|
* that Linux can map all of its PA space to the PCI bus.
|
|
* Use the IOMMU to handle hash-for-home memory.
|
|
*/
|
|
for_each_online_node(j) {
|
|
unsigned long start_pfn = node_start_pfn[j];
|
|
unsigned long end_pfn = node_end_pfn[j];
|
|
unsigned long nr_pages = end_pfn - start_pfn;
|
|
|
|
ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0,
|
|
0);
|
|
if (ret < 0) {
|
|
pr_err("PCI: Mem-Map alloc failure on TRIO %d "
|
|
"mac %d for MC %d, give up\n",
|
|
controller->trio_index,
|
|
controller->mac, j);
|
|
|
|
goto alloc_mem_map_failed;
|
|
}
|
|
|
|
controller->mem_maps[j] = ret;
|
|
|
|
/*
|
|
* Initialize the Mem-Map and the I/O MMU so that all
|
|
* the physical memory can be accessed by the endpoint
|
|
* devices. The base bus address is set to the base CPA
|
|
* of this memory controller plus an offset (see pci.h).
|
|
* The region's base VA is set to the base CPA. The
|
|
* I/O MMU table essentially translates the CPA to
|
|
* the real PA. Implicitly, for node 0, we create
|
|
* a separate Mem-Map region that serves as the inbound
|
|
* window for legacy 32-bit devices. This is a direct
|
|
* map of the low 4GB CPA space.
|
|
*/
|
|
ret = gxio_trio_init_memory_map_mmu_aux(trio_context,
|
|
controller->mem_maps[j],
|
|
start_pfn << PAGE_SHIFT,
|
|
nr_pages << PAGE_SHIFT,
|
|
trio_context->asid,
|
|
controller->mac,
|
|
(start_pfn << PAGE_SHIFT) +
|
|
TILE_PCI_MEM_MAP_BASE_OFFSET,
|
|
j,
|
|
GXIO_TRIO_ORDER_MODE_UNORDERED);
|
|
if (ret < 0) {
|
|
pr_err("PCI: Mem-Map init failure on TRIO %d "
|
|
"mac %d for MC %d, give up\n",
|
|
controller->trio_index,
|
|
controller->mac, j);
|
|
|
|
goto alloc_mem_map_failed;
|
|
}
|
|
continue;
|
|
|
|
alloc_mem_map_failed:
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
subsys_initcall(pcibios_init);
|
|
|
|
/* No bus fixups needed. */
|
|
void pcibios_fixup_bus(struct pci_bus *bus)
|
|
{
|
|
}
|
|
|
|
/* Process any "pci=" kernel boot arguments. */
|
|
char *__init pcibios_setup(char *str)
|
|
{
|
|
if (!strcmp(str, "off")) {
|
|
pci_probe = 0;
|
|
return NULL;
|
|
}
|
|
return str;
|
|
}
|
|
|
|
/*
|
|
* Called for each device after PCI setup is done.
|
|
* We initialize the PCI device capabilities conservatively, assuming that
|
|
* all devices can only address the 32-bit DMA space. The exception here is
|
|
* that the device dma_offset is set to the value that matches the 64-bit
|
|
* capable devices. This is OK because dma_offset is not used by legacy
|
|
* dma_ops, nor by the hybrid dma_ops's streaming DMAs, which are 64-bit ops.
|
|
* This implementation matches the kernel design of setting PCI devices'
|
|
* coherent_dma_mask to 0xffffffffull by default, allowing the device drivers
|
|
* to skip calling pci_set_consistent_dma_mask(DMA_BIT_MASK(32)).
|
|
*/
|
|
static void pcibios_fixup_final(struct pci_dev *pdev)
|
|
{
|
|
set_dma_ops(&pdev->dev, gx_legacy_pci_dma_map_ops);
|
|
set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET);
|
|
pdev->dev.archdata.max_direct_dma_addr =
|
|
TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
|
|
pdev->dev.coherent_dma_mask = TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
|
|
|
|
/* Map a PCI MMIO bus address into VA space. */
|
|
void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
|
|
{
|
|
struct pci_controller *controller = NULL;
|
|
resource_size_t bar_start;
|
|
resource_size_t bar_end;
|
|
resource_size_t offset;
|
|
resource_size_t start;
|
|
resource_size_t end;
|
|
int trio_fd;
|
|
int i;
|
|
|
|
start = phys_addr;
|
|
end = phys_addr + size - 1;
|
|
|
|
/*
|
|
* By searching phys_addr in each controller's mem_space, we can
|
|
* determine the controller that should accept the PCI memory access.
|
|
*/
|
|
for (i = 0; i < num_rc_controllers; i++) {
|
|
/*
|
|
* Skip controllers that are not properly initialized or
|
|
* have down links.
|
|
*/
|
|
if (pci_controllers[i].root_bus == NULL)
|
|
continue;
|
|
|
|
bar_start = pci_controllers[i].mem_space.start;
|
|
bar_end = pci_controllers[i].mem_space.end;
|
|
|
|
if ((start >= bar_start) && (end <= bar_end)) {
|
|
controller = &pci_controllers[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (controller == NULL)
|
|
return NULL;
|
|
|
|
trio_fd = controller->trio->fd;
|
|
|
|
/* Convert the resource start to the bus address offset. */
|
|
start = phys_addr - controller->mem_offset;
|
|
|
|
offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start;
|
|
|
|
/* We need to keep the PCI bus address's in-page offset in the VA. */
|
|
return iorpc_ioremap(trio_fd, offset, size) +
|
|
(start & (PAGE_SIZE - 1));
|
|
}
|
|
EXPORT_SYMBOL(ioremap);
|
|
|
|
#ifdef CONFIG_TILE_PCI_IO
|
|
/* Map a PCI I/O address into VA space. */
|
|
void __iomem *ioport_map(unsigned long port, unsigned int size)
|
|
{
|
|
struct pci_controller *controller = NULL;
|
|
resource_size_t bar_start;
|
|
resource_size_t bar_end;
|
|
resource_size_t offset;
|
|
resource_size_t start;
|
|
resource_size_t end;
|
|
int trio_fd;
|
|
int i;
|
|
|
|
start = port;
|
|
end = port + size - 1;
|
|
|
|
/*
|
|
* By searching the port in each controller's io_space, we can
|
|
* determine the controller that should accept the PCI I/O access.
|
|
*/
|
|
for (i = 0; i < num_rc_controllers; i++) {
|
|
/*
|
|
* Skip controllers that are not properly initialized or
|
|
* have down links.
|
|
*/
|
|
if (pci_controllers[i].root_bus == NULL)
|
|
continue;
|
|
|
|
bar_start = pci_controllers[i].io_space.start;
|
|
bar_end = pci_controllers[i].io_space.end;
|
|
|
|
if ((start >= bar_start) && (end <= bar_end)) {
|
|
controller = &pci_controllers[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (controller == NULL)
|
|
return NULL;
|
|
|
|
trio_fd = controller->trio->fd;
|
|
|
|
/* Convert the resource start to the bus address offset. */
|
|
port -= controller->io_space.start;
|
|
|
|
offset = HV_TRIO_PIO_OFFSET(controller->pio_io_index) + port;
|
|
|
|
/* We need to keep the PCI bus address's in-page offset in the VA. */
|
|
return iorpc_ioremap(trio_fd, offset, size) + (port & (PAGE_SIZE - 1));
|
|
}
|
|
EXPORT_SYMBOL(ioport_map);
|
|
|
|
void ioport_unmap(void __iomem *addr)
|
|
{
|
|
iounmap(addr);
|
|
}
|
|
EXPORT_SYMBOL(ioport_unmap);
|
|
#endif
|
|
|
|
void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
|
|
{
|
|
iounmap(addr);
|
|
}
|
|
EXPORT_SYMBOL(pci_iounmap);
|
|
|
|
/****************************************************************
|
|
*
|
|
* Tile PCI config space read/write routines
|
|
*
|
|
****************************************************************/
|
|
|
|
/*
|
|
* These are the normal read and write ops
|
|
* These are expanded with macros from pci_bus_read_config_byte() etc.
|
|
*
|
|
* devfn is the combined PCI device & function.
|
|
*
|
|
* offset is in bytes, from the start of config space for the
|
|
* specified bus & device.
|
|
*/
|
|
static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
|
|
int size, u32 *val)
|
|
{
|
|
struct pci_controller *controller = bus->sysdata;
|
|
gxio_trio_context_t *trio_context = controller->trio;
|
|
int busnum = bus->number & 0xff;
|
|
int device = PCI_SLOT(devfn);
|
|
int function = PCI_FUNC(devfn);
|
|
int config_type = 1;
|
|
TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
|
|
void *mmio_addr;
|
|
|
|
/*
|
|
* Map all accesses to the local device on root bus into the
|
|
* MMIO space of the MAC. Accesses to the downstream devices
|
|
* go to the PIO space.
|
|
*/
|
|
if (pci_is_root_bus(bus)) {
|
|
if (device == 0) {
|
|
/*
|
|
* This is the internal downstream P2P bridge,
|
|
* access directly.
|
|
*/
|
|
unsigned int reg_offset;
|
|
|
|
reg_offset = ((offset & 0xFFF) <<
|
|
TRIO_CFG_REGION_ADDR__REG_SHIFT) |
|
|
(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
|
|
<< TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
|
|
(controller->mac <<
|
|
TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
|
|
|
|
mmio_addr = trio_context->mmio_base_mac + reg_offset;
|
|
|
|
goto valid_device;
|
|
|
|
} else {
|
|
/*
|
|
* We fake an empty device for (device > 0),
|
|
* since there is only one device on bus 0.
|
|
*/
|
|
goto invalid_device;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Accesses to the directly attached device have to be
|
|
* sent as type-0 configs.
|
|
*/
|
|
if (busnum == (controller->first_busno + 1)) {
|
|
/*
|
|
* There is only one device off of our built-in P2P bridge.
|
|
*/
|
|
if (device != 0)
|
|
goto invalid_device;
|
|
|
|
config_type = 0;
|
|
}
|
|
|
|
cfg_addr.word = 0;
|
|
cfg_addr.reg_addr = (offset & 0xFFF);
|
|
cfg_addr.fn = function;
|
|
cfg_addr.dev = device;
|
|
cfg_addr.bus = busnum;
|
|
cfg_addr.type = config_type;
|
|
|
|
/*
|
|
* Note that we don't set the mac field in cfg_addr because the
|
|
* mapping is per port.
|
|
*/
|
|
mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
|
|
cfg_addr.word;
|
|
|
|
valid_device:
|
|
|
|
switch (size) {
|
|
case 4:
|
|
*val = __gxio_mmio_read32(mmio_addr);
|
|
break;
|
|
|
|
case 2:
|
|
*val = __gxio_mmio_read16(mmio_addr);
|
|
break;
|
|
|
|
case 1:
|
|
*val = __gxio_mmio_read8(mmio_addr);
|
|
break;
|
|
|
|
default:
|
|
return PCIBIOS_FUNC_NOT_SUPPORTED;
|
|
}
|
|
|
|
TRACE_CFG_RD(size, *val, busnum, device, function, offset);
|
|
|
|
return 0;
|
|
|
|
invalid_device:
|
|
|
|
switch (size) {
|
|
case 4:
|
|
*val = 0xFFFFFFFF;
|
|
break;
|
|
|
|
case 2:
|
|
*val = 0xFFFF;
|
|
break;
|
|
|
|
case 1:
|
|
*val = 0xFF;
|
|
break;
|
|
|
|
default:
|
|
return PCIBIOS_FUNC_NOT_SUPPORTED;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* See tile_cfg_read() for relevent comments.
|
|
* Note that "val" is the value to write, not a pointer to that value.
|
|
*/
|
|
static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
|
|
int size, u32 val)
|
|
{
|
|
struct pci_controller *controller = bus->sysdata;
|
|
gxio_trio_context_t *trio_context = controller->trio;
|
|
int busnum = bus->number & 0xff;
|
|
int device = PCI_SLOT(devfn);
|
|
int function = PCI_FUNC(devfn);
|
|
int config_type = 1;
|
|
TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
|
|
void *mmio_addr;
|
|
u32 val_32 = (u32)val;
|
|
u16 val_16 = (u16)val;
|
|
u8 val_8 = (u8)val;
|
|
|
|
/*
|
|
* Map all accesses to the local device on root bus into the
|
|
* MMIO space of the MAC. Accesses to the downstream devices
|
|
* go to the PIO space.
|
|
*/
|
|
if (pci_is_root_bus(bus)) {
|
|
if (device == 0) {
|
|
/*
|
|
* This is the internal downstream P2P bridge,
|
|
* access directly.
|
|
*/
|
|
unsigned int reg_offset;
|
|
|
|
reg_offset = ((offset & 0xFFF) <<
|
|
TRIO_CFG_REGION_ADDR__REG_SHIFT) |
|
|
(TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
|
|
<< TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
|
|
(controller->mac <<
|
|
TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
|
|
|
|
mmio_addr = trio_context->mmio_base_mac + reg_offset;
|
|
|
|
goto valid_device;
|
|
|
|
} else {
|
|
/*
|
|
* We fake an empty device for (device > 0),
|
|
* since there is only one device on bus 0.
|
|
*/
|
|
goto invalid_device;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Accesses to the directly attached device have to be
|
|
* sent as type-0 configs.
|
|
*/
|
|
if (busnum == (controller->first_busno + 1)) {
|
|
/*
|
|
* There is only one device off of our built-in P2P bridge.
|
|
*/
|
|
if (device != 0)
|
|
goto invalid_device;
|
|
|
|
config_type = 0;
|
|
}
|
|
|
|
cfg_addr.word = 0;
|
|
cfg_addr.reg_addr = (offset & 0xFFF);
|
|
cfg_addr.fn = function;
|
|
cfg_addr.dev = device;
|
|
cfg_addr.bus = busnum;
|
|
cfg_addr.type = config_type;
|
|
|
|
/*
|
|
* Note that we don't set the mac field in cfg_addr because the
|
|
* mapping is per port.
|
|
*/
|
|
mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
|
|
cfg_addr.word;
|
|
|
|
valid_device:
|
|
|
|
switch (size) {
|
|
case 4:
|
|
__gxio_mmio_write32(mmio_addr, val_32);
|
|
TRACE_CFG_WR(size, val_32, busnum, device, function, offset);
|
|
break;
|
|
|
|
case 2:
|
|
__gxio_mmio_write16(mmio_addr, val_16);
|
|
TRACE_CFG_WR(size, val_16, busnum, device, function, offset);
|
|
break;
|
|
|
|
case 1:
|
|
__gxio_mmio_write8(mmio_addr, val_8);
|
|
TRACE_CFG_WR(size, val_8, busnum, device, function, offset);
|
|
break;
|
|
|
|
default:
|
|
return PCIBIOS_FUNC_NOT_SUPPORTED;
|
|
}
|
|
|
|
invalid_device:
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static struct pci_ops tile_cfg_ops = {
|
|
.read = tile_cfg_read,
|
|
.write = tile_cfg_write,
|
|
};
|
|
|
|
|
|
/* MSI support starts here. */
|
|
static unsigned int tilegx_msi_startup(struct irq_data *d)
|
|
{
|
|
if (d->msi_desc)
|
|
unmask_msi_irq(d);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tilegx_msi_ack(struct irq_data *d)
|
|
{
|
|
__insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
|
|
}
|
|
|
|
static void tilegx_msi_mask(struct irq_data *d)
|
|
{
|
|
mask_msi_irq(d);
|
|
__insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
|
|
}
|
|
|
|
static void tilegx_msi_unmask(struct irq_data *d)
|
|
{
|
|
__insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
|
|
unmask_msi_irq(d);
|
|
}
|
|
|
|
static struct irq_chip tilegx_msi_chip = {
|
|
.name = "tilegx_msi",
|
|
.irq_startup = tilegx_msi_startup,
|
|
.irq_ack = tilegx_msi_ack,
|
|
.irq_mask = tilegx_msi_mask,
|
|
.irq_unmask = tilegx_msi_unmask,
|
|
|
|
/* TBD: support set_affinity. */
|
|
};
|
|
|
|
int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
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{
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struct pci_controller *controller;
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gxio_trio_context_t *trio_context;
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struct msi_msg msg;
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int default_irq;
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uint64_t mem_map_base;
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uint64_t mem_map_limit;
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u64 msi_addr;
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int mem_map;
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int cpu;
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int irq;
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int ret;
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irq = irq_alloc_hwirq(-1);
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if (!irq)
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return -ENOSPC;
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/*
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* Since we use a 64-bit Mem-Map to accept the MSI write, we fail
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* devices that are not capable of generating a 64-bit message address.
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* These devices will fall back to using the legacy interrupts.
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* Most PCIe endpoint devices do support 64-bit message addressing.
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*/
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if (desc->msi_attrib.is_64 == 0) {
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dev_printk(KERN_INFO, &pdev->dev,
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"64-bit MSI message address not supported, "
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"falling back to legacy interrupts.\n");
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ret = -ENOMEM;
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goto is_64_failure;
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}
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default_irq = desc->msi_attrib.default_irq;
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controller = irq_get_handler_data(default_irq);
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BUG_ON(!controller);
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|
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trio_context = controller->trio;
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|
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/*
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* Allocate a scatter-queue that will accept the MSI write and
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* trigger the TILE-side interrupts. We use the scatter-queue regions
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* before the mem map regions, because the latter are needed by more
|
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* applications.
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*/
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mem_map = gxio_trio_alloc_scatter_queues(trio_context, 1, 0, 0);
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if (mem_map >= 0) {
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TRIO_MAP_SQ_DOORBELL_FMT_t doorbell_template = {{
|
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.pop = 0,
|
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.doorbell = 1,
|
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}};
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|
|
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mem_map += TRIO_NUM_MAP_MEM_REGIONS;
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mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
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mem_map * MEM_MAP_INTR_REGION_SIZE;
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mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
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|
|
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msi_addr = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 8;
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msg.data = (unsigned int)doorbell_template.word;
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} else {
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/* SQ regions are out, allocate from map mem regions. */
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mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0);
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if (mem_map < 0) {
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dev_printk(KERN_INFO, &pdev->dev,
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"%s Mem-Map alloc failure. "
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"Failed to initialize MSI interrupts. "
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"Falling back to legacy interrupts.\n",
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desc->msi_attrib.is_msix ? "MSI-X" : "MSI");
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ret = -ENOMEM;
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goto msi_mem_map_alloc_failure;
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}
|
|
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mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
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mem_map * MEM_MAP_INTR_REGION_SIZE;
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mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
|
|
|
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msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 -
|
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TRIO_MAP_MEM_REG_INT0;
|
|
|
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msg.data = mem_map;
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}
|
|
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/* We try to distribute different IRQs to different tiles. */
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cpu = tile_irq_cpu(irq);
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/*
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* Now call up to the HV to configure the MSI interrupt and
|
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* set up the IPI binding.
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*/
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ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu),
|
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KERNEL_PL, irq, controller->mac,
|
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mem_map, mem_map_base, mem_map_limit,
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trio_context->asid);
|
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if (ret < 0) {
|
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dev_printk(KERN_INFO, &pdev->dev, "HV MSI config failed.\n");
|
|
|
|
goto hv_msi_config_failure;
|
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}
|
|
|
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irq_set_msi_desc(irq, desc);
|
|
|
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msg.address_hi = msi_addr >> 32;
|
|
msg.address_lo = msi_addr & 0xffffffff;
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|
|
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write_msi_msg(irq, &msg);
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irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
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irq_set_handler_data(irq, controller);
|
|
|
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return 0;
|
|
|
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hv_msi_config_failure:
|
|
/* Free mem-map */
|
|
msi_mem_map_alloc_failure:
|
|
is_64_failure:
|
|
irq_free_hwirq(irq);
|
|
return ret;
|
|
}
|
|
|
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void arch_teardown_msi_irq(unsigned int irq)
|
|
{
|
|
irq_free_hwirq(irq);
|
|
}
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