![Linus Torvalds](/assets/img/avatar_default.png)
Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEABECAAYFAlSOD20ACgkQMUfUDdst+ylLPACg2QrW1oHhdTMT9WI8jihlHVRM 53kAoLeteByQ3iVwWurwwseRPiWa8+MI =OVRS -----END PGP SIGNATURE----- Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
966 lines
23 KiB
C
966 lines
23 KiB
C
/*
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* Freescale SPI controller driver.
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*
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* Maintainer: Kumar Gala
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*
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* Copyright (C) 2006 Polycom, Inc.
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* CPM SPI and QE buffer descriptors mode support:
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* GRLIB support:
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* Copyright (c) 2012 Aeroflex Gaisler AB.
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* Author: Andreas Larsson <andreas@gaisler.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/fsl_devices.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_gpio.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/types.h>
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#include "spi-fsl-lib.h"
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#include "spi-fsl-cpm.h"
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#include "spi-fsl-spi.h"
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#define TYPE_FSL 0
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#define TYPE_GRLIB 1
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struct fsl_spi_match_data {
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int type;
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};
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static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
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.type = TYPE_FSL,
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};
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static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
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.type = TYPE_GRLIB,
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};
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static const struct of_device_id of_fsl_spi_match[] = {
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{
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.compatible = "fsl,spi",
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.data = &of_fsl_spi_fsl_config,
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},
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{
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.compatible = "aeroflexgaisler,spictrl",
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.data = &of_fsl_spi_grlib_config,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
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static int fsl_spi_get_type(struct device *dev)
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{
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const struct of_device_id *match;
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if (dev->of_node) {
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match = of_match_node(of_fsl_spi_match, dev->of_node);
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if (match && match->data)
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return ((struct fsl_spi_match_data *)match->data)->type;
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}
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return TYPE_FSL;
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}
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static void fsl_spi_change_mode(struct spi_device *spi)
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{
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struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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struct fsl_spi_reg *reg_base = mspi->reg_base;
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__be32 __iomem *mode = ®_base->mode;
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unsigned long flags;
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if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
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return;
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/* Turn off IRQs locally to minimize time that SPI is disabled. */
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
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/* When in CPM mode, we need to reinit tx and rx. */
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if (mspi->flags & SPI_CPM_MODE) {
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fsl_spi_cpm_reinit_txrx(mspi);
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}
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mpc8xxx_spi_write_reg(mode, cs->hw_mode);
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local_irq_restore(flags);
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}
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static void fsl_spi_chipselect(struct spi_device *spi, int value)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct fsl_spi_platform_data *pdata;
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bool pol = spi->mode & SPI_CS_HIGH;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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pdata = spi->dev.parent->parent->platform_data;
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if (value == BITBANG_CS_INACTIVE) {
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if (pdata->cs_control)
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pdata->cs_control(spi, !pol);
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}
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if (value == BITBANG_CS_ACTIVE) {
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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fsl_spi_change_mode(spi);
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if (pdata->cs_control)
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pdata->cs_control(spi, pol);
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}
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}
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static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
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int bits_per_word, int msb_first)
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{
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*rx_shift = 0;
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*tx_shift = 0;
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if (msb_first) {
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if (bits_per_word <= 8) {
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*rx_shift = 16;
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*tx_shift = 24;
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} else if (bits_per_word <= 16) {
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*rx_shift = 16;
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*tx_shift = 16;
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}
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} else {
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if (bits_per_word <= 8)
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*rx_shift = 8;
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}
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}
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static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
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int bits_per_word, int msb_first)
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{
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*rx_shift = 0;
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*tx_shift = 0;
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if (bits_per_word <= 16) {
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if (msb_first) {
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*rx_shift = 16; /* LSB in bit 16 */
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*tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
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} else {
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*rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
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}
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}
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}
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static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
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struct spi_device *spi,
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struct mpc8xxx_spi *mpc8xxx_spi,
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int bits_per_word)
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{
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cs->rx_shift = 0;
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cs->tx_shift = 0;
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if (bits_per_word <= 8) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u8;
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cs->get_tx = mpc8xxx_spi_tx_buf_u8;
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} else if (bits_per_word <= 16) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u16;
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cs->get_tx = mpc8xxx_spi_tx_buf_u16;
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} else if (bits_per_word <= 32) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u32;
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cs->get_tx = mpc8xxx_spi_tx_buf_u32;
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} else
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return -EINVAL;
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if (mpc8xxx_spi->set_shifts)
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mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
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bits_per_word,
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!(spi->mode & SPI_LSB_FIRST));
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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return bits_per_word;
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}
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static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
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struct spi_device *spi,
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int bits_per_word)
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{
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/* QE uses Little Endian for words > 8
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* so transform all words > 8 into 8 bits
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* Unfortnatly that doesn't work for LSB so
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* reject these for now */
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/* Note: 32 bits word, LSB works iff
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* tfcr/rfcr is set to CPMFCR_GBL */
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if (spi->mode & SPI_LSB_FIRST &&
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bits_per_word > 8)
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return -EINVAL;
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if (bits_per_word > 8)
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return 8; /* pretend its 8 bits */
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return bits_per_word;
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}
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static int fsl_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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int bits_per_word = 0;
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u8 pm;
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u32 hz = 0;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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if (t) {
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bits_per_word = t->bits_per_word;
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hz = t->speed_hz;
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}
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/* spi_transfer level calls that work per-word */
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if (!bits_per_word)
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bits_per_word = spi->bits_per_word;
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if (!hz)
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hz = spi->max_speed_hz;
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if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
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bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
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mpc8xxx_spi,
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bits_per_word);
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else if (mpc8xxx_spi->flags & SPI_QE)
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bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
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bits_per_word);
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if (bits_per_word < 0)
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return bits_per_word;
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if (bits_per_word == 32)
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bits_per_word = 0;
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else
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bits_per_word = bits_per_word - 1;
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
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| SPMODE_PM(0xF));
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cs->hw_mode |= SPMODE_LEN(bits_per_word);
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if ((mpc8xxx_spi->spibrg / hz) > 64) {
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cs->hw_mode |= SPMODE_DIV16;
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pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
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WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
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"Will use %d Hz instead.\n", dev_name(&spi->dev),
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hz, mpc8xxx_spi->spibrg / 1024);
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if (pm > 16)
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pm = 16;
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} else {
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pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
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}
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if (pm)
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pm--;
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cs->hw_mode |= SPMODE_PM(pm);
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fsl_spi_change_mode(spi);
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return 0;
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}
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static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
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struct spi_transfer *t, unsigned int len)
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{
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u32 word;
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struct fsl_spi_reg *reg_base = mspi->reg_base;
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mspi->count = len;
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/* enable rx ints */
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mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
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/* transmit word */
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word = mspi->get_tx(mspi);
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mpc8xxx_spi_write_reg(®_base->transmit, word);
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return 0;
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}
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static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
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bool is_dma_mapped)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct fsl_spi_reg *reg_base;
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unsigned int len = t->len;
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u8 bits_per_word;
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int ret;
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reg_base = mpc8xxx_spi->reg_base;
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bits_per_word = spi->bits_per_word;
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if (t->bits_per_word)
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bits_per_word = t->bits_per_word;
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if (bits_per_word > 8) {
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/* invalid length? */
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if (len & 1)
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return -EINVAL;
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len /= 2;
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}
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if (bits_per_word > 16) {
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/* invalid length? */
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if (len & 1)
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return -EINVAL;
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len /= 2;
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}
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mpc8xxx_spi->tx = t->tx_buf;
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mpc8xxx_spi->rx = t->rx_buf;
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reinit_completion(&mpc8xxx_spi->done);
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if (mpc8xxx_spi->flags & SPI_CPM_MODE)
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ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
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else
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ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
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if (ret)
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return ret;
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wait_for_completion(&mpc8xxx_spi->done);
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/* disable rx ints */
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mpc8xxx_spi_write_reg(®_base->mask, 0);
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if (mpc8xxx_spi->flags & SPI_CPM_MODE)
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fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
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return mpc8xxx_spi->count;
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}
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static int fsl_spi_do_one_msg(struct spi_master *master,
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struct spi_message *m)
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{
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struct spi_device *spi = m->spi;
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struct spi_transfer *t, *first;
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unsigned int cs_change;
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const int nsecs = 50;
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int status;
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/* Don't allow changes if CS is active */
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first = list_first_entry(&m->transfers, struct spi_transfer,
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transfer_list);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if ((first->bits_per_word != t->bits_per_word) ||
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(first->speed_hz != t->speed_hz)) {
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dev_err(&spi->dev,
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"bits_per_word/speed_hz should be same for the same SPI transfer\n");
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return -EINVAL;
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}
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}
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cs_change = 1;
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status = -EINVAL;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->bits_per_word || t->speed_hz) {
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if (cs_change)
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status = fsl_spi_setup_transfer(spi, t);
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if (status < 0)
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break;
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}
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if (cs_change) {
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fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
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ndelay(nsecs);
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}
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cs_change = t->cs_change;
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if (t->len)
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status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
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if (status) {
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status = -EMSGSIZE;
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break;
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}
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m->actual_length += t->len;
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (cs_change) {
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ndelay(nsecs);
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fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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ndelay(nsecs);
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}
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}
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m->status = status;
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spi_finalize_current_message(master);
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if (status || !cs_change) {
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ndelay(nsecs);
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fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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}
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fsl_spi_setup_transfer(spi, NULL);
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return 0;
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}
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|
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static int fsl_spi_setup(struct spi_device *spi)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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struct fsl_spi_reg *reg_base;
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int retval;
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u32 hw_mode;
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struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
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|
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if (!spi->max_speed_hz)
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return -EINVAL;
|
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|
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if (!cs) {
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cs = kzalloc(sizeof(*cs), GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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spi_set_ctldata(spi, cs);
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}
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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reg_base = mpc8xxx_spi->reg_base;
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hw_mode = cs->hw_mode; /* Save original settings */
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cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode);
|
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
|
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| SPMODE_REV | SPMODE_LOOP);
|
|
|
|
if (spi->mode & SPI_CPHA)
|
|
cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
|
|
if (spi->mode & SPI_CPOL)
|
|
cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
|
|
if (!(spi->mode & SPI_LSB_FIRST))
|
|
cs->hw_mode |= SPMODE_REV;
|
|
if (spi->mode & SPI_LOOP)
|
|
cs->hw_mode |= SPMODE_LOOP;
|
|
|
|
retval = fsl_spi_setup_transfer(spi, NULL);
|
|
if (retval < 0) {
|
|
cs->hw_mode = hw_mode; /* Restore settings */
|
|
return retval;
|
|
}
|
|
|
|
if (mpc8xxx_spi->type == TYPE_GRLIB) {
|
|
if (gpio_is_valid(spi->cs_gpio)) {
|
|
int desel;
|
|
|
|
retval = gpio_request(spi->cs_gpio,
|
|
dev_name(&spi->dev));
|
|
if (retval)
|
|
return retval;
|
|
|
|
desel = !(spi->mode & SPI_CS_HIGH);
|
|
retval = gpio_direction_output(spi->cs_gpio, desel);
|
|
if (retval) {
|
|
gpio_free(spi->cs_gpio);
|
|
return retval;
|
|
}
|
|
} else if (spi->cs_gpio != -ENOENT) {
|
|
if (spi->cs_gpio < 0)
|
|
return spi->cs_gpio;
|
|
return -EINVAL;
|
|
}
|
|
/* When spi->cs_gpio == -ENOENT, a hole in the phandle list
|
|
* indicates to use native chipselect if present, or allow for
|
|
* an always selected chip
|
|
*/
|
|
}
|
|
|
|
/* Initialize chipselect - might be active for SPI_CS_HIGH mode */
|
|
fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void fsl_spi_cleanup(struct spi_device *spi)
|
|
{
|
|
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
|
|
struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
|
|
|
|
if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
|
|
gpio_free(spi->cs_gpio);
|
|
|
|
kfree(cs);
|
|
spi_set_ctldata(spi, NULL);
|
|
}
|
|
|
|
static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
|
|
{
|
|
struct fsl_spi_reg *reg_base = mspi->reg_base;
|
|
|
|
/* We need handle RX first */
|
|
if (events & SPIE_NE) {
|
|
u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
|
|
|
|
if (mspi->rx)
|
|
mspi->get_rx(rx_data, mspi);
|
|
}
|
|
|
|
if ((events & SPIE_NF) == 0)
|
|
/* spin until TX is done */
|
|
while (((events =
|
|
mpc8xxx_spi_read_reg(®_base->event)) &
|
|
SPIE_NF) == 0)
|
|
cpu_relax();
|
|
|
|
/* Clear the events */
|
|
mpc8xxx_spi_write_reg(®_base->event, events);
|
|
|
|
mspi->count -= 1;
|
|
if (mspi->count) {
|
|
u32 word = mspi->get_tx(mspi);
|
|
|
|
mpc8xxx_spi_write_reg(®_base->transmit, word);
|
|
} else {
|
|
complete(&mspi->done);
|
|
}
|
|
}
|
|
|
|
static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
|
|
{
|
|
struct mpc8xxx_spi *mspi = context_data;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
u32 events;
|
|
struct fsl_spi_reg *reg_base = mspi->reg_base;
|
|
|
|
/* Get interrupt events(tx/rx) */
|
|
events = mpc8xxx_spi_read_reg(®_base->event);
|
|
if (events)
|
|
ret = IRQ_HANDLED;
|
|
|
|
dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
|
|
|
|
if (mspi->flags & SPI_CPM_MODE)
|
|
fsl_spi_cpm_irq(mspi, events);
|
|
else
|
|
fsl_spi_cpu_irq(mspi, events);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
|
|
{
|
|
iounmap(mspi->reg_base);
|
|
fsl_spi_cpm_free(mspi);
|
|
}
|
|
|
|
static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
|
|
{
|
|
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
|
|
struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
|
|
u32 slvsel;
|
|
u16 cs = spi->chip_select;
|
|
|
|
if (gpio_is_valid(spi->cs_gpio)) {
|
|
gpio_set_value(spi->cs_gpio, on);
|
|
} else if (cs < mpc8xxx_spi->native_chipselects) {
|
|
slvsel = mpc8xxx_spi_read_reg(®_base->slvsel);
|
|
slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
|
|
mpc8xxx_spi_write_reg(®_base->slvsel, slvsel);
|
|
}
|
|
}
|
|
|
|
static void fsl_spi_grlib_probe(struct device *dev)
|
|
{
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
|
|
struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
|
|
int mbits;
|
|
u32 capabilities;
|
|
|
|
capabilities = mpc8xxx_spi_read_reg(®_base->cap);
|
|
|
|
mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
|
|
mbits = SPCAP_MAXWLEN(capabilities);
|
|
if (mbits)
|
|
mpc8xxx_spi->max_bits_per_word = mbits + 1;
|
|
|
|
mpc8xxx_spi->native_chipselects = 0;
|
|
if (SPCAP_SSEN(capabilities)) {
|
|
mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
|
|
mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff);
|
|
}
|
|
master->num_chipselect = mpc8xxx_spi->native_chipselects;
|
|
pdata->cs_control = fsl_spi_grlib_cs_control;
|
|
}
|
|
|
|
static struct spi_master * fsl_spi_probe(struct device *dev,
|
|
struct resource *mem, unsigned int irq)
|
|
{
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
struct spi_master *master;
|
|
struct mpc8xxx_spi *mpc8xxx_spi;
|
|
struct fsl_spi_reg *reg_base;
|
|
u32 regval;
|
|
int ret = 0;
|
|
|
|
master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
|
|
if (master == NULL) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
dev_set_drvdata(dev, master);
|
|
|
|
mpc8xxx_spi_probe(dev, mem, irq);
|
|
|
|
master->setup = fsl_spi_setup;
|
|
master->cleanup = fsl_spi_cleanup;
|
|
master->transfer_one_message = fsl_spi_do_one_msg;
|
|
|
|
mpc8xxx_spi = spi_master_get_devdata(master);
|
|
mpc8xxx_spi->spi_remove = fsl_spi_remove;
|
|
mpc8xxx_spi->max_bits_per_word = 32;
|
|
mpc8xxx_spi->type = fsl_spi_get_type(dev);
|
|
|
|
ret = fsl_spi_cpm_init(mpc8xxx_spi);
|
|
if (ret)
|
|
goto err_cpm_init;
|
|
|
|
mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
|
|
if (mpc8xxx_spi->reg_base == NULL) {
|
|
ret = -ENOMEM;
|
|
goto err_ioremap;
|
|
}
|
|
|
|
if (mpc8xxx_spi->type == TYPE_GRLIB)
|
|
fsl_spi_grlib_probe(dev);
|
|
|
|
master->bits_per_word_mask =
|
|
(SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
|
|
SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
|
|
|
|
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
|
|
mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
|
|
|
|
if (mpc8xxx_spi->set_shifts)
|
|
/* 8 bits per word and MSB first */
|
|
mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
|
|
&mpc8xxx_spi->tx_shift, 8, 1);
|
|
|
|
/* Register for SPI Interrupt */
|
|
ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
|
|
0, "fsl_spi", mpc8xxx_spi);
|
|
|
|
if (ret != 0)
|
|
goto free_irq;
|
|
|
|
reg_base = mpc8xxx_spi->reg_base;
|
|
|
|
/* SPI controller initializations */
|
|
mpc8xxx_spi_write_reg(®_base->mode, 0);
|
|
mpc8xxx_spi_write_reg(®_base->mask, 0);
|
|
mpc8xxx_spi_write_reg(®_base->command, 0);
|
|
mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
|
|
|
|
/* Enable SPI interface */
|
|
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
|
|
if (mpc8xxx_spi->max_bits_per_word < 8) {
|
|
regval &= ~SPMODE_LEN(0xF);
|
|
regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
|
|
}
|
|
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
|
|
regval |= SPMODE_OP;
|
|
|
|
mpc8xxx_spi_write_reg(®_base->mode, regval);
|
|
|
|
ret = spi_register_master(master);
|
|
if (ret < 0)
|
|
goto unreg_master;
|
|
|
|
dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
|
|
mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
|
|
|
|
return master;
|
|
|
|
unreg_master:
|
|
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
|
|
free_irq:
|
|
iounmap(mpc8xxx_spi->reg_base);
|
|
err_ioremap:
|
|
fsl_spi_cpm_free(mpc8xxx_spi);
|
|
err_cpm_init:
|
|
spi_master_put(master);
|
|
err:
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
static void fsl_spi_cs_control(struct spi_device *spi, bool on)
|
|
{
|
|
struct device *dev = spi->dev.parent->parent;
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
|
|
u16 cs = spi->chip_select;
|
|
int gpio = pinfo->gpios[cs];
|
|
bool alow = pinfo->alow_flags[cs];
|
|
|
|
gpio_set_value(gpio, on ^ alow);
|
|
}
|
|
|
|
static int of_fsl_spi_get_chipselects(struct device *dev)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
|
|
int ngpios;
|
|
int i = 0;
|
|
int ret;
|
|
|
|
ngpios = of_gpio_count(np);
|
|
if (ngpios <= 0) {
|
|
/*
|
|
* SPI w/o chip-select line. One SPI device is still permitted
|
|
* though.
|
|
*/
|
|
pdata->max_chipselect = 1;
|
|
return 0;
|
|
}
|
|
|
|
pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
|
|
if (!pinfo->gpios)
|
|
return -ENOMEM;
|
|
memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
|
|
|
|
pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
|
|
GFP_KERNEL);
|
|
if (!pinfo->alow_flags) {
|
|
ret = -ENOMEM;
|
|
goto err_alloc_flags;
|
|
}
|
|
|
|
for (; i < ngpios; i++) {
|
|
int gpio;
|
|
enum of_gpio_flags flags;
|
|
|
|
gpio = of_get_gpio_flags(np, i, &flags);
|
|
if (!gpio_is_valid(gpio)) {
|
|
dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
|
|
ret = gpio;
|
|
goto err_loop;
|
|
}
|
|
|
|
ret = gpio_request(gpio, dev_name(dev));
|
|
if (ret) {
|
|
dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
|
|
goto err_loop;
|
|
}
|
|
|
|
pinfo->gpios[i] = gpio;
|
|
pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
|
|
|
|
ret = gpio_direction_output(pinfo->gpios[i],
|
|
pinfo->alow_flags[i]);
|
|
if (ret) {
|
|
dev_err(dev, "can't set output direction for gpio "
|
|
"#%d: %d\n", i, ret);
|
|
goto err_loop;
|
|
}
|
|
}
|
|
|
|
pdata->max_chipselect = ngpios;
|
|
pdata->cs_control = fsl_spi_cs_control;
|
|
|
|
return 0;
|
|
|
|
err_loop:
|
|
while (i >= 0) {
|
|
if (gpio_is_valid(pinfo->gpios[i]))
|
|
gpio_free(pinfo->gpios[i]);
|
|
i--;
|
|
}
|
|
|
|
kfree(pinfo->alow_flags);
|
|
pinfo->alow_flags = NULL;
|
|
err_alloc_flags:
|
|
kfree(pinfo->gpios);
|
|
pinfo->gpios = NULL;
|
|
return ret;
|
|
}
|
|
|
|
static int of_fsl_spi_free_chipselects(struct device *dev)
|
|
{
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
|
|
int i;
|
|
|
|
if (!pinfo->gpios)
|
|
return 0;
|
|
|
|
for (i = 0; i < pdata->max_chipselect; i++) {
|
|
if (gpio_is_valid(pinfo->gpios[i]))
|
|
gpio_free(pinfo->gpios[i]);
|
|
}
|
|
|
|
kfree(pinfo->gpios);
|
|
kfree(pinfo->alow_flags);
|
|
return 0;
|
|
}
|
|
|
|
static int of_fsl_spi_probe(struct platform_device *ofdev)
|
|
{
|
|
struct device *dev = &ofdev->dev;
|
|
struct device_node *np = ofdev->dev.of_node;
|
|
struct spi_master *master;
|
|
struct resource mem;
|
|
int irq, type;
|
|
int ret = -ENOMEM;
|
|
|
|
ret = of_mpc8xxx_spi_probe(ofdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
type = fsl_spi_get_type(&ofdev->dev);
|
|
if (type == TYPE_FSL) {
|
|
ret = of_fsl_spi_get_chipselects(dev);
|
|
if (ret)
|
|
goto err;
|
|
}
|
|
|
|
ret = of_address_to_resource(np, 0, &mem);
|
|
if (ret)
|
|
goto err;
|
|
|
|
irq = irq_of_parse_and_map(np, 0);
|
|
if (!irq) {
|
|
ret = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
master = fsl_spi_probe(dev, &mem, irq);
|
|
if (IS_ERR(master)) {
|
|
ret = PTR_ERR(master);
|
|
goto err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
if (type == TYPE_FSL)
|
|
of_fsl_spi_free_chipselects(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int of_fsl_spi_remove(struct platform_device *ofdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(ofdev);
|
|
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
|
|
int ret;
|
|
|
|
ret = mpc8xxx_spi_remove(&ofdev->dev);
|
|
if (ret)
|
|
return ret;
|
|
if (mpc8xxx_spi->type == TYPE_FSL)
|
|
of_fsl_spi_free_chipselects(&ofdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver of_fsl_spi_driver = {
|
|
.driver = {
|
|
.name = "fsl_spi",
|
|
.of_match_table = of_fsl_spi_match,
|
|
},
|
|
.probe = of_fsl_spi_probe,
|
|
.remove = of_fsl_spi_remove,
|
|
};
|
|
|
|
#ifdef CONFIG_MPC832x_RDB
|
|
/*
|
|
* XXX XXX XXX
|
|
* This is "legacy" platform driver, was used by the MPC8323E-RDB boards
|
|
* only. The driver should go away soon, since newer MPC8323E-RDB's device
|
|
* tree can work with OpenFirmware driver. But for now we support old trees
|
|
* as well.
|
|
*/
|
|
static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *mem;
|
|
int irq;
|
|
struct spi_master *master;
|
|
|
|
if (!dev_get_platdata(&pdev->dev))
|
|
return -EINVAL;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!mem)
|
|
return -EINVAL;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq <= 0)
|
|
return -EINVAL;
|
|
|
|
master = fsl_spi_probe(&pdev->dev, mem, irq);
|
|
return PTR_ERR_OR_ZERO(master);
|
|
}
|
|
|
|
static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
|
|
{
|
|
return mpc8xxx_spi_remove(&pdev->dev);
|
|
}
|
|
|
|
MODULE_ALIAS("platform:mpc8xxx_spi");
|
|
static struct platform_driver mpc8xxx_spi_driver = {
|
|
.probe = plat_mpc8xxx_spi_probe,
|
|
.remove = plat_mpc8xxx_spi_remove,
|
|
.driver = {
|
|
.name = "mpc8xxx_spi",
|
|
},
|
|
};
|
|
|
|
static bool legacy_driver_failed;
|
|
|
|
static void __init legacy_driver_register(void)
|
|
{
|
|
legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
|
|
}
|
|
|
|
static void __exit legacy_driver_unregister(void)
|
|
{
|
|
if (legacy_driver_failed)
|
|
return;
|
|
platform_driver_unregister(&mpc8xxx_spi_driver);
|
|
}
|
|
#else
|
|
static void __init legacy_driver_register(void) {}
|
|
static void __exit legacy_driver_unregister(void) {}
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#endif /* CONFIG_MPC832x_RDB */
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static int __init fsl_spi_init(void)
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{
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legacy_driver_register();
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return platform_driver_register(&of_fsl_spi_driver);
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}
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module_init(fsl_spi_init);
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static void __exit fsl_spi_exit(void)
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{
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platform_driver_unregister(&of_fsl_spi_driver);
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legacy_driver_unregister();
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}
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module_exit(fsl_spi_exit);
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MODULE_AUTHOR("Kumar Gala");
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MODULE_DESCRIPTION("Simple Freescale SPI Driver");
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MODULE_LICENSE("GPL");
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