47ebed96ff
Pull networking fixes from David Miller:
1) mlx4 driver bug fixes (TX queue wakeups, csum complete indications)
from Ido Shamay, Eran Ben Elisha, and Or Gerlitz.
2) Missing unlock in error path of PTP support in renesas driver, from
Dan Carpenter.
3) Add Vitesse 8641 phy IDs to vitesse PHY driver, from Shaohui Xie.
4) Bnx2x driver bug fixes (linearization of encap packets, scratchpad
parity error notifications, flow-control and speed settings) from
Yuval Mintz, Manish Chopra, Shahed Shaikh, and Ariel Elior.
5) ipv6 extension header parsing in the igb chip has a HW errata,
disable it. Frm Todd Fujinaka.
6) Fix PCI link state locking issue in e1000e driver, from Yanir
Lubetkin.
7) Cure panics during MTU change in i40e, from Mitch Williams.
8) Don't leak promisc refs in DSA slave driver, from Gilad Ben-Yossef.
9) Add missing HAS_DMA dep to VIA Rhine driver, from Geery
Uytterhoeven.
10) Make sure DMA map/unmap calls are symmetric in bnx2x driver, from
Michal Schmidt.
11) Workaround for MDIO access problems in bcm7xxx devices, from FLorian
Fainelli.
12) Fix races in SCTP protocol between OTTB responses and route
removals, from Alexander Sverdlin.
13) Fix jumbo frame checksum issue with some mvneta devices, from Simon
Guinot.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (58 commits)
sock_diag: don't broadcast kernel sockets
net: mvneta: disable IP checksum with jumbo frames for Armada 370
ARM: mvebu: update Ethernet compatible string for Armada XP
net: mvneta: introduce compatible string "marvell, armada-xp-neta"
api: fix compatibility of linux/in.h with netinet/in.h
net: icplus: fix typo in constant name
sis900: Trivial: Fix typos in enums
stmmac: Trivial: fix typo in constant name
sctp: Fix race between OOTB responce and route removal
net-Liquidio: Delete unnecessary checks before the function call "vfree"
vmxnet3: Bump up driver version number
amd-xgbe: Add the __GFP_NOWARN flag to Rx buffer allocation
net: phy: mdio-bcm-unimac: workaround initial read failures for integrated PHYs
net: bcmgenet: workaround initial read failures for integrated PHYs
net: phy: bcm7xxx: workaround MDIO management controller initial read
bnx2x: fix DMA API usage
net: via: VIA_RHINE and VIA_VELOCITY should depend on HAS_DMA
net/phy: tune get_phy_c45_ids to support more c45 phy
bnx2x: fix lockdep splat
net: fec: don't access RACC register when not available
...
413 lines
10 KiB
Plaintext
413 lines
10 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada 370 family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Contains definitions specific to the Armada 370 SoC that are not
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* common to all Armada SoCs.
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*/
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#include "armada-370-xp.dtsi"
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/include/ "skeleton.dtsi"
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/ {
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model = "Marvell Armada 370 family SoC";
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compatible = "marvell,armada370", "marvell,armada-370-xp";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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soc {
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compatible = "marvell,armada370-mbus", "simple-bus";
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
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};
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pcie-controller {
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compatible = "marvell,armada-370-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
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0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
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0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
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0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 62>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 9>;
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status = "disabled";
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};
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};
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internal-regs {
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L2: l2-cache {
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compatible = "marvell,aurora-outer-cache";
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reg = <0x08000 0x1000>;
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cache-id-part = <0x100>;
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cache-level = <2>;
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cache-unified;
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wt-override;
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};
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/*
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* Default SPI pinctrl setting, can be overwritten on
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* board level if a different configuration is used.
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*/
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spi0: spi@10600 {
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compatible = "marvell,armada-370-spi",
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"marvell,orion-spi";
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pinctrl-0 = <&spi0_pins1>;
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pinctrl-names = "default";
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};
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spi1: spi@10680 {
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compatible = "marvell,armada-370-spi",
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"marvell,orion-spi";
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pinctrl-0 = <&spi1_pins>;
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pinctrl-names = "default";
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};
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i2c0: i2c@11000 {
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reg = <0x11000 0x20>;
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};
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i2c1: i2c@11100 {
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reg = <0x11100 0x20>;
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <82>, <83>, <84>, <85>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,orion-gpio";
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reg = <0x18140 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <87>, <88>, <89>, <90>;
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};
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gpio2: gpio@18180 {
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compatible = "marvell,orion-gpio";
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reg = <0x18180 0x40>;
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ngpios = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <91>;
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};
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/*
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* Default UART pinctrl setting without RTS/CTS, can
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* be overwritten on board level if a different
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* configuration is used.
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*/
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uart0: serial@12000 {
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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};
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uart1: serial@12100 {
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pinctrl-0 = <&uart1_pins>;
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pinctrl-names = "default";
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};
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system-controller@18200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0x18200 0x100>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,armada-370-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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coreclk: mvebu-sar@18230 {
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compatible = "marvell,armada-370-core-clock";
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reg = <0x18230 0x08>;
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#clock-cells = <1>;
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};
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thermal@18300 {
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compatible = "marvell,armada370-thermal";
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reg = <0x18300 0x4
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0x18304 0x4>;
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status = "okay";
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};
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sscg@18330 {
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reg = <0x18330 0x4>;
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};
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interrupt-controller@20a00 {
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reg = <0x20a00 0x1d0>, <0x21870 0x58>;
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};
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timer@20300 {
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compatible = "marvell,armada-370-timer";
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clocks = <&coreclk 2>;
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};
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watchdog@20300 {
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compatible = "marvell,armada-370-wdt";
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clocks = <&coreclk 2>;
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};
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cpurst@20800 {
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compatible = "marvell,armada-370-cpu-reset";
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reg = <0x20800 0x8>;
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};
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audio_controller: audio-controller@30000 {
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#sound-dai-cells = <1>;
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compatible = "marvell,armada370-audio";
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reg = <0x30000 0x4000>;
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interrupts = <93>;
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clocks = <&gateclk 0>;
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clock-names = "internal";
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status = "disabled";
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};
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usb@50000 {
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clocks = <&coreclk 0>;
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};
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usb@51000 {
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clocks = <&coreclk 0>;
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};
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xor@60800 {
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compatible = "marvell,orion-xor";
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reg = <0x60800 0x100
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0x60A00 0x100>;
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status = "okay";
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xor00 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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xor@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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status = "okay";
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xor10 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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ethernet@70000 {
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compatible = "marvell,armada-370-neta";
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};
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ethernet@74000 {
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compatible = "marvell,armada-370-neta";
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};
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};
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};
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};
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&pinctrl {
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compatible = "marvell,mv88f6710-pinctrl";
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spi0_pins1: spi0-pins1 {
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marvell,pins = "mpp33", "mpp34",
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"mpp35", "mpp36";
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marvell,function = "spi0";
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};
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spi0_pins2: spi0_pins2 {
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marvell,pins = "mpp32", "mpp63",
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"mpp64", "mpp65";
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marvell,function = "spi0";
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};
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spi1_pins: spi1-pins {
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marvell,pins = "mpp49", "mpp50",
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"mpp51", "mpp52";
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marvell,function = "spi1";
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};
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uart0_pins: uart0-pins {
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marvell,pins = "mpp0", "mpp1";
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marvell,function = "uart0";
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};
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uart1_pins: uart1-pins {
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marvell,pins = "mpp41", "mpp42";
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marvell,function = "uart1";
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};
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sdio_pins1: sdio-pins1 {
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marvell,pins = "mpp9", "mpp11", "mpp12",
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"mpp13", "mpp14", "mpp15";
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marvell,function = "sd0";
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};
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sdio_pins2: sdio-pins2 {
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marvell,pins = "mpp47", "mpp48", "mpp49",
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"mpp50", "mpp51", "mpp52";
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marvell,function = "sd0";
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};
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sdio_pins3: sdio-pins3 {
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marvell,pins = "mpp48", "mpp49", "mpp50",
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"mpp51", "mpp52", "mpp53";
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marvell,function = "sd0";
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};
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i2c0_pins: i2c0-pins {
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marvell,pins = "mpp2", "mpp3";
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marvell,function = "i2c0";
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};
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i2s_pins1: i2s-pins1 {
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marvell,pins = "mpp5", "mpp6", "mpp7",
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"mpp8", "mpp9", "mpp10",
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"mpp12", "mpp13";
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marvell,function = "audio";
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};
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i2s_pins2: i2s-pins2 {
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marvell,pins = "mpp49", "mpp47", "mpp50",
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"mpp59", "mpp57", "mpp61",
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"mpp62", "mpp60", "mpp58";
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marvell,function = "audio";
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};
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mdio_pins: mdio-pins {
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marvell,pins = "mpp17", "mpp18";
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marvell,function = "ge";
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};
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ge0_rgmii_pins: ge0-rgmii-pins {
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marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
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"mpp9", "mpp10", "mpp11", "mpp12",
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"mpp13", "mpp14", "mpp15", "mpp16";
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marvell,function = "ge0";
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};
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ge1_rgmii_pins: ge1-rgmii-pins {
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marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
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"mpp23", "mpp24", "mpp25", "mpp26",
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"mpp27", "mpp28", "mpp29", "mpp30";
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marvell,function = "ge1";
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};
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};
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