1215baa7a3
There exists a tiny MMU, configurable only by the VC (running the closed firmware), which maps from the ARM's physical addresses to bus addresses. These bus addresses determine the caching behavior in the VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top 2 bits. The bits in the bus address mean: From the VideoCore processor: 0x0... L1 and L2 cache allocating and coherent 0x4... L1 non-allocating, but coherent. L2 allocating and coherent 0x8... L1 non-allocating, but coherent. L2 non-allocating, but coherent 0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent From the GPU peripherals (note: all peripherals bypass the L1 cache. The ARM will see this view once through the VC MMU): 0x0... Do not use 0x4... L1 non-allocating, and incoherent. L2 allocating and coherent. 0x8... L1 non-allocating, and incoherent. L2 non-allocating, but coherent 0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent The 2835 firmware always configures the MMU to turn ARM physical addresses with 0x0 top bits to 0x4, meaning present in L2 but incoherent with L1. However, any bus addresses we were generating in the kernel to be passed to a device had 0x0 bits. That would be a reserved (possibly totally incoherent) value if sent to a GPU peripheral like USB, or L1 allocating if sent to the VC (like a firmware property request). By setting dma-ranges, all of the devices below it get a dev->dma_pfn_offset, so that dma_alloc_coherent() and friends return addresses with 0x4 bits and avoid cache incoherency. This matches the behavior in the downstream 2708 kernel (see BUS_OFFSET in arch/arm/mach-bcm2708/include/mach/memory.h). Signed-off-by: Eric Anholt <eric@anholt.net> Tested-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
193 lines
4 KiB
Plaintext
193 lines
4 KiB
Plaintext
#include <dt-bindings/pinctrl/bcm2835.h>
|
|
#include "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "brcm,bcm2835";
|
|
model = "BCM2835";
|
|
interrupt-parent = <&intc>;
|
|
|
|
chosen {
|
|
bootargs = "earlyprintk console=ttyAMA0";
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x7e000000 0x20000000 0x02000000>;
|
|
dma-ranges = <0x40000000 0x00000000 0x20000000>;
|
|
|
|
timer@7e003000 {
|
|
compatible = "brcm,bcm2835-system-timer";
|
|
reg = <0x7e003000 0x1000>;
|
|
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
|
|
clock-frequency = <1000000>;
|
|
};
|
|
|
|
dma: dma@7e007000 {
|
|
compatible = "brcm,bcm2835-dma";
|
|
reg = <0x7e007000 0xf00>;
|
|
interrupts = <1 16>,
|
|
<1 17>,
|
|
<1 18>,
|
|
<1 19>,
|
|
<1 20>,
|
|
<1 21>,
|
|
<1 22>,
|
|
<1 23>,
|
|
<1 24>,
|
|
<1 25>,
|
|
<1 26>,
|
|
<1 27>,
|
|
<1 28>;
|
|
|
|
#dma-cells = <1>;
|
|
brcm,dma-channel-mask = <0x7f35>;
|
|
};
|
|
|
|
intc: interrupt-controller@7e00b200 {
|
|
compatible = "brcm,bcm2835-armctrl-ic";
|
|
reg = <0x7e00b200 0x200>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
watchdog@7e100000 {
|
|
compatible = "brcm,bcm2835-pm-wdt";
|
|
reg = <0x7e100000 0x28>;
|
|
};
|
|
|
|
rng@7e104000 {
|
|
compatible = "brcm,bcm2835-rng";
|
|
reg = <0x7e104000 0x10>;
|
|
};
|
|
|
|
mailbox: mailbox@7e00b800 {
|
|
compatible = "brcm,bcm2835-mbox";
|
|
reg = <0x7e00b880 0x40>;
|
|
interrupts = <0 1>;
|
|
#mbox-cells = <0>;
|
|
};
|
|
|
|
gpio: gpio@7e200000 {
|
|
compatible = "brcm,bcm2835-gpio";
|
|
reg = <0x7e200000 0xb4>;
|
|
/*
|
|
* The GPIO IP block is designed for 3 banks of GPIOs.
|
|
* Each bank has a GPIO interrupt for itself.
|
|
* There is an overall "any bank" interrupt.
|
|
* In order, these are GIC interrupts 17, 18, 19, 20.
|
|
* Since the BCM2835 only has 2 banks, the 2nd bank
|
|
* interrupt output appears to be mirrored onto the
|
|
* 3rd bank's interrupt signal.
|
|
* So, a bank0 interrupt shows up on 17, 20, and
|
|
* a bank1 interrupt shows up on 18, 19, 20!
|
|
*/
|
|
interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
uart@7e201000 {
|
|
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
|
reg = <0x7e201000 0x1000>;
|
|
interrupts = <2 25>;
|
|
clock-frequency = <3000000>;
|
|
arm,primecell-periphid = <0x00241011>;
|
|
};
|
|
|
|
i2s: i2s@7e203000 {
|
|
compatible = "brcm,bcm2835-i2s";
|
|
reg = <0x7e203000 0x20>,
|
|
<0x7e101098 0x02>;
|
|
|
|
dmas = <&dma 2>,
|
|
<&dma 3>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi: spi@7e204000 {
|
|
compatible = "brcm,bcm2835-spi";
|
|
reg = <0x7e204000 0x1000>;
|
|
interrupts = <2 22>;
|
|
clocks = <&clk_spi>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@7e205000 {
|
|
compatible = "brcm,bcm2835-i2c";
|
|
reg = <0x7e205000 0x1000>;
|
|
interrupts = <2 21>;
|
|
clocks = <&clk_i2c>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci: sdhci@7e300000 {
|
|
compatible = "brcm,bcm2835-sdhci";
|
|
reg = <0x7e300000 0x100>;
|
|
interrupts = <2 30>;
|
|
clocks = <&clk_mmc>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@7e804000 {
|
|
compatible = "brcm,bcm2835-i2c";
|
|
reg = <0x7e804000 0x1000>;
|
|
interrupts = <2 21>;
|
|
clocks = <&clk_i2c>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7e980000 {
|
|
compatible = "brcm,bcm2835-usb";
|
|
reg = <0x7e980000 0x10000>;
|
|
interrupts = <1 9>;
|
|
};
|
|
|
|
arm-pmu {
|
|
compatible = "arm,arm1176-pmu";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
clk_mmc: clock@0 {
|
|
compatible = "fixed-clock";
|
|
reg = <0>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "mmc";
|
|
clock-frequency = <100000000>;
|
|
};
|
|
|
|
clk_i2c: clock@1 {
|
|
compatible = "fixed-clock";
|
|
reg = <1>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "i2c";
|
|
clock-frequency = <250000000>;
|
|
};
|
|
|
|
clk_spi: clock@2 {
|
|
compatible = "fixed-clock";
|
|
reg = <2>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "spi";
|
|
clock-frequency = <250000000>;
|
|
};
|
|
};
|
|
};
|