b5399ea845
The four port serial port on the zoom debug board uses a TL16CP754C with a single interrupt and GPMC chip select. The serial ports each use a 8 bytes for IO registers, and are 256 bytes apart on the GPMC line. Let's add timings for all four ports so we can remove the GPMC workarounds for using bootloader timings. Not caused by this patch, but looks like u-boot only properly initializes the fifo on the first serial port. Currently the other ports produce garbage at least with my version of u-boot. I suspect that TL16CP754C needs non-standard initialization added to 8250 driver to properly fix this issue. Cc: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
92 lines
2.3 KiB
Plaintext
92 lines
2.3 KiB
Plaintext
/*
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* Common features on the Zoom debug board
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*/
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#include "omap-gpmc-smsc911x.dtsi"
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&gpmc {
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ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */
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<7 0 0x2c000000 0x01000000>;
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/*
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* Four port TL16CP754C serial port on GPMC,
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* they probably share the same GPIO IRQ
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* REVISIT: Add timing support from slls644g.pdf
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*/
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uart@3,0 {
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compatible = "ns16550a";
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reg = <3 0 8>; /* CS3, offset 0, IO size 8 */
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bank-width = <2>;
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reg-shift = <1>;
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reg-io-width = <1>;
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interrupt-parent = <&gpio4>;
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interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
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clock-frequency = <1843200>;
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current-speed = <115200>;
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gpmc,mux-add-data = <0>;
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gpmc,device-width = <1>;
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gpmc,wait-pin = <1>;
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gpmc,cycle2cycle-samecsen = <1>;
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gpmc,cycle2cycle-diffcsen = <1>;
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gpmc,cs-on-ns = <5>;
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gpmc,cs-rd-off-ns = <155>;
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gpmc,cs-wr-off-ns = <155>;
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gpmc,adv-on-ns = <15>;
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gpmc,adv-rd-off-ns = <40>;
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gpmc,adv-wr-off-ns = <40>;
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gpmc,oe-on-ns = <45>;
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gpmc,oe-off-ns = <145>;
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gpmc,we-on-ns = <45>;
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gpmc,we-off-ns = <145>;
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gpmc,rd-cycle-ns = <155>;
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gpmc,wr-cycle-ns = <155>;
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gpmc,access-ns = <145>;
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gpmc,page-burst-access-ns = <20>;
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gpmc,bus-turnaround-ns = <20>;
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gpmc,cycle2cycle-delay-ns = <20>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wr-data-mux-bus-ns = <45>;
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gpmc,wr-access-ns = <145>;
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};
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uart@3,1 {
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compatible = "ns16550a";
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reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */
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bank-width = <2>;
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reg-shift = <1>;
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reg-io-width = <1>;
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interrupt-parent = <&gpio4>;
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interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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uart@3,2 {
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compatible = "ns16550a";
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reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */
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bank-width = <2>;
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reg-shift = <1>;
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reg-io-width = <1>;
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interrupt-parent = <&gpio4>;
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interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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uart@3,3 {
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compatible = "ns16550a";
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reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */
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bank-width = <2>;
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reg-shift = <1>;
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reg-io-width = <1>;
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interrupt-parent = <&gpio4>;
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interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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ethernet@gpmc {
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reg = <7 0 0xff>;
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interrupt-parent = <&gpio5>;
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interrupts = <30 IRQ_TYPE_LEVEL_LOW>; /* gpio158 */
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};
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};
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