9512c6fec8
The DSS fclk and iclk handles are named differently on OMAP3430 ES1 than on later OMAP revisions. The ES1 has handles 'dss1_alwon_fck_3430es1' and 'dss_ick_3430es1', whereas later revisions have similar names but ending with 'es2'. This means we don't have one clock handle to which we could refer to when defining the DSS clocks. However, as the namespaces are separate for ES1 and ES2+ OMAPs, we can just rename the handles to 'dss1_alwon_fck' and 'dss_ick' for both ES1 and ES2+, removing the issue. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com> Tested-by: Marek Belisko <marek@goldelico.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
243 lines
5.3 KiB
Plaintext
243 lines
5.3 KiB
Plaintext
/*
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* Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&prm_clocks {
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corex2_d3_fck: corex2_d3_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&corex2_fck>;
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clock-mult = <1>;
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clock-div = <3>;
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};
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corex2_d5_fck: corex2_d5_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&corex2_fck>;
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clock-mult = <1>;
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clock-div = <5>;
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};
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};
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&cm_clocks {
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dpll5_ck: dpll5_ck {
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#clock-cells = <0>;
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compatible = "ti,omap3-dpll-clock";
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clocks = <&sys_ck>, <&sys_ck>;
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reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
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ti,low-power-stop;
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ti,lock;
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};
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dpll5_m2_ck: dpll5_m2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll5_ck>;
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ti,max-div = <31>;
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reg = <0x0d50>;
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ti,index-starts-at-one;
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};
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sgx_gate_fck: sgx_gate_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <1>;
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reg = <0x0b00>;
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};
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core_d3_ck: core_d3_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <3>;
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};
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core_d4_ck: core_d4_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <4>;
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};
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core_d6_ck: core_d6_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <6>;
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};
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omap_192m_alwon_fck: omap_192m_alwon_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll4_m2x2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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core_d2_ck: core_d2_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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sgx_mux_fck: sgx_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
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reg = <0x0b40>;
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};
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sgx_fck: sgx_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
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};
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sgx_ick: sgx_ick {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&l3_ick>;
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reg = <0x0b10>;
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ti,bit-shift = <0>;
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};
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cpefuse_fck: cpefuse_fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_ck>;
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reg = <0x0a08>;
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ti,bit-shift = <0>;
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};
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ts_fck: ts_fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&omap_32k_fck>;
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reg = <0x0a08>;
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ti,bit-shift = <1>;
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};
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usbtll_fck: usbtll_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&dpll5_m2_ck>;
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reg = <0x0a08>;
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ti,bit-shift = <2>;
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};
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usbtll_ick: usbtll_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l4_ick>;
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reg = <0x0a18>;
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ti,bit-shift = <2>;
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};
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mmchs3_ick: mmchs3_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <30>;
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};
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mmchs3_fck: mmchs3_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&core_96m_fck>;
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reg = <0x0a00>;
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ti,bit-shift = <30>;
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};
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dss1_alwon_fck: dss1_alwon_fck_3430es2 {
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#clock-cells = <0>;
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compatible = "ti,dss-gate-clock";
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clocks = <&dpll4_m4x2_ck>;
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ti,bit-shift = <0>;
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reg = <0x0e00>;
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ti,set-rate-parent;
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};
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dss_ick: dss_ick_3430es2 {
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#clock-cells = <0>;
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compatible = "ti,omap3-dss-interface-clock";
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clocks = <&l4_ick>;
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reg = <0x0e10>;
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ti,bit-shift = <0>;
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};
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usbhost_120m_fck: usbhost_120m_fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll5_m2_ck>;
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reg = <0x1400>;
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ti,bit-shift = <1>;
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};
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usbhost_48m_fck: usbhost_48m_fck {
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#clock-cells = <0>;
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compatible = "ti,dss-gate-clock";
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clocks = <&omap_48m_fck>;
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reg = <0x1400>;
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ti,bit-shift = <0>;
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};
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usbhost_ick: usbhost_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-dss-interface-clock";
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clocks = <&l4_ick>;
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reg = <0x1410>;
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ti,bit-shift = <0>;
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};
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};
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&cm_clockdomains {
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dpll5_clkdm: dpll5_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dpll5_ck>;
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};
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sgx_clkdm: sgx_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&sgx_ick>;
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};
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dss_clkdm: dss_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
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<&dss1_alwon_fck>, <&dss_ick>;
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};
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core_l4_clkdm: core_l4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
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<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
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<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
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<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
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<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
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<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
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<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
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<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
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<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
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<&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
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<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
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};
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usbhost_clkdm: usbhost_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
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<&usbhost_ick>;
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};
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};
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