![Bjorn Helgaas](/assets/img/avatar_default.png)
All the DesignWare-based host drivers loop waiting for the link to come up, but they do it several ways that are needlessly different. Wait for the link to come up in a consistent style across all the DesignWare drivers. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
181 lines
4 KiB
C
181 lines
4 KiB
C
/*
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* PCIe host controller driver for Freescale Layerscape SoCs
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*
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* Copyright (C) 2014 Freescale Semiconductor.
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*
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* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pcie-designware.h"
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/* PEX1/2 Misc Ports Status Register */
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#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
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#define LTSSM_STATE_SHIFT 20
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#define LTSSM_STATE_MASK 0x3f
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#define LTSSM_PCIE_L0 0x11 /* L0 state */
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/* Symbol Timer Register and Filter Mask Register 1 */
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#define PCIE_STRFMR1 0x71c
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struct ls_pcie {
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struct list_head node;
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struct device *dev;
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struct pci_bus *bus;
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void __iomem *dbi;
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struct regmap *scfg;
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struct pcie_port pp;
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int index;
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int msi_irq;
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};
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#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
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static int ls_pcie_link_up(struct pcie_port *pp)
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{
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u32 state;
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struct ls_pcie *pcie = to_ls_pcie(pp);
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regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
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state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0)
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return 0;
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return 1;
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}
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static int ls_pcie_establish_link(struct pcie_port *pp)
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{
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unsigned int retries;
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for (retries = 0; retries < 200; retries++) {
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if (dw_pcie_link_up(pp))
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return 0;
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usleep_range(100, 1000);
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}
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dev_err(pp->dev, "phy link never came up\n");
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return -EINVAL;
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}
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static void ls_pcie_host_init(struct pcie_port *pp)
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{
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struct ls_pcie *pcie = to_ls_pcie(pp);
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u32 val;
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dw_pcie_setup_rc(pp);
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ls_pcie_establish_link(pp);
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/*
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* LS1021A Workaround for internal TKT228622
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* to fix the INTx hang issue
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*/
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val = ioread32(pcie->dbi + PCIE_STRFMR1);
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val &= 0xffff;
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iowrite32(val, pcie->dbi + PCIE_STRFMR1);
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}
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static struct pcie_host_ops ls_pcie_host_ops = {
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.link_up = ls_pcie_link_up,
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.host_init = ls_pcie_host_init,
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};
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static int ls_add_pcie_port(struct ls_pcie *pcie)
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{
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struct pcie_port *pp;
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int ret;
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pp = &pcie->pp;
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pp->dev = pcie->dev;
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pp->dbi_base = pcie->dbi;
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pp->root_bus_nr = -1;
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pp->ops = &ls_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(pp->dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int __init ls_pcie_probe(struct platform_device *pdev)
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{
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struct ls_pcie *pcie;
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struct resource *dbi_base;
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u32 index[2];
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int ret;
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pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pcie->dev = &pdev->dev;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
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if (IS_ERR(pcie->dbi)) {
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dev_err(&pdev->dev, "missing *regs* space\n");
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return PTR_ERR(pcie->dbi);
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}
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pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"fsl,pcie-scfg");
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if (IS_ERR(pcie->scfg)) {
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dev_err(&pdev->dev, "No syscfg phandle specified\n");
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return PTR_ERR(pcie->scfg);
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}
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ret = of_property_read_u32_array(pdev->dev.of_node,
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"fsl,pcie-scfg", index, 2);
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if (ret)
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return ret;
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pcie->index = index[1];
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ret = ls_add_pcie_port(pcie);
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if (ret < 0)
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return ret;
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platform_set_drvdata(pdev, pcie);
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return 0;
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}
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static const struct of_device_id ls_pcie_of_match[] = {
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{ .compatible = "fsl,ls1021a-pcie" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
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static struct platform_driver ls_pcie_driver = {
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.driver = {
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.name = "layerscape-pcie",
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.of_match_table = ls_pcie_of_match,
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},
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};
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module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
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MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
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MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
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MODULE_LICENSE("GPL v2");
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