088dd1f81b
This allows a PCI controller to shim into IRQ delivery so that DMA queues can be drained, if necessary. If some bus specific code needs to run before an IRQ handler is invoked, the bus driver simply needs to setup the function pointer in bucket->irq_info->pre_handler and the two args bucket->irq_info->pre_handler_arg[12]. The Schizo PCI driver is converted over to use a pre-handler for the DMA write-sync processing it needs when a device is behind a PCI->PCI bus deeper than the top-level APB bridges. While we're here, clean up all of the action allocation and handling. Now, we allocate the irqaction as part of the bucket->irq_info area. There is an array of 4 irqaction (for PCI irq sharing) and a bitmask saying which entries are active. The bucket->irq_info is allocated at build_irq() time, not at request_irq() time. This simplifies request_irq() and free_irq() tremendously. The SMP dynamic IRQ retargetting code got removed in this change too. It was disabled for a few months now, and we can resurrect it in the future if we want. Signed-off-by: David S. Miller <davem@davemloft.net>
144 lines
4 KiB
C
144 lines
4 KiB
C
/* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $
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* irq.h: IRQ registers on the 64-bit Sparc.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#ifndef _SPARC64_IRQ_H
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#define _SPARC64_IRQ_H
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <asm/pil.h>
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#include <asm/ptrace.h>
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struct ino_bucket;
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#define MAX_IRQ_DESC_ACTION 4
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struct irq_desc {
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void (*pre_handler)(struct ino_bucket *, void *, void *);
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void *pre_handler_arg1;
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void *pre_handler_arg2;
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u32 action_active_mask;
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struct irqaction action[MAX_IRQ_DESC_ACTION];
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};
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/* You should not mess with this directly. That's the job of irq.c.
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*
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* If you make changes here, please update hand coded assembler of
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* the vectored interrupt trap handler in entry.S -DaveM
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*
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* This is currently one DCACHE line, two buckets per L2 cache
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* line. Keep this in mind please.
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*/
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struct ino_bucket {
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/* Next handler in per-CPU PIL worklist. We know that
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* bucket pointers have the high 32-bits clear, so to
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* save space we only store the bits we need.
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*/
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/*0x00*/unsigned int irq_chain;
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/* PIL to schedule this IVEC at. */
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/*0x04*/unsigned char pil;
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/* If an IVEC arrives while irq_info is NULL, we
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* set this to notify request_irq() about the event.
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*/
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/*0x05*/unsigned char pending;
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/* Miscellaneous flags. */
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/*0x06*/unsigned char flags;
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/* Currently unused. */
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/*0x07*/unsigned char __pad;
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/* Reference to IRQ descriptor for this bucket. */
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/*0x08*/struct irq_desc *irq_info;
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/* Sun5 Interrupt Clear Register. */
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/*0x10*/unsigned long iclr;
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/* Sun5 Interrupt Mapping Register. */
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/*0x18*/unsigned long imap;
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};
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/* IMAP/ICLR register defines */
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#define IMAP_VALID 0x80000000 /* IRQ Enabled */
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#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
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#define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */
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#define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */
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#define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */
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#define IMAP_IGN 0x000007c0 /* IRQ Group Number */
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#define IMAP_INO 0x0000003f /* IRQ Number */
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#define IMAP_INR 0x000007ff /* Full interrupt number*/
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#define ICLR_IDLE 0x00000000 /* Idle state */
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#define ICLR_TRANSMIT 0x00000001 /* Transmit state */
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#define ICLR_PENDING 0x00000003 /* Pending state */
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/* Only 8-bits are available, be careful. -DaveM */
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#define IBF_PCI 0x02 /* PSYCHO/SABRE/SCHIZO PCI interrupt. */
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#define IBF_ACTIVE 0x04 /* Interrupt is active and has a handler.*/
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#define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */
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#define NUM_IVECS (IMAP_INR + 1)
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extern struct ino_bucket ivector_table[NUM_IVECS];
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#define __irq_ino(irq) \
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(((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
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#define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
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#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
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#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
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static __inline__ char *__irq_itoa(unsigned int irq)
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{
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static char buff[16];
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sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
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return buff;
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}
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#define NR_IRQS 16
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#define irq_canonicalize(irq) (irq)
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extern void disable_irq(unsigned int);
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#define disable_irq_nosync disable_irq
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extern void enable_irq(unsigned int);
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extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
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extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
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static __inline__ void set_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%set_softint"
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: /* No outputs */
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: "r" (bits));
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}
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static __inline__ void clear_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%clear_softint"
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: /* No outputs */
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: "r" (bits));
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}
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static __inline__ unsigned long get_softint(void)
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{
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unsigned long retval;
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__asm__ __volatile__("rd %%softint, %0"
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: "=r" (retval));
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return retval;
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}
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struct irqaction;
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struct pt_regs;
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int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
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#endif
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