![cpw@sgi.com](/assets/img/avatar_default.png)
Correct the UV2 broacast assist unit's destination timeout period. And the activation status register in UV2 should be tested for a destination timeout with a 4, not a 2. The values for Active versus Timeout were reversed. This patch is critical for TLB shootdown on an Altix UV2 system (i.e. the follow-on to the current Altix UV). Destination timeout period: The period is set in 4 bits of memory-mapped register MISC_CONTROL. The left bit toggles base period between 10us and 80us. The other 3 bits are the multiplier. Decimal 15, hex f, gives the maximum: 7 * 80us Signed-off-by: Cliff Wickman <cpw@sgi.com> Link: http://lkml.kernel.org/r/20110621122243.117324443@sgi.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
689 lines
21 KiB
C
689 lines
21 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV Broadcast Assist Unit definitions
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*
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* Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_X86_UV_UV_BAU_H
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#define _ASM_X86_UV_UV_BAU_H
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#include <linux/bitmap.h>
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#define BITSPERBYTE 8
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/*
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* Broadcast Assist Unit messaging structures
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*
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* Selective Broadcast activations are induced by software action
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* specifying a particular 8-descriptor "set" via a 6-bit index written
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* to an MMR.
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* Thus there are 64 unique 512-byte sets of SB descriptors - one set for
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* each 6-bit index value. These descriptor sets are mapped in sequence
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* starting with set 0 located at the address specified in the
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* BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
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* set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
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*
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* We will use one set for sending BAU messages from each of the
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* cpu's on the uvhub.
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*
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* TLB shootdown will use the first of the 8 descriptors of each set.
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* Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
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*/
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#define MAX_CPUS_PER_UVHUB 64
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#define MAX_CPUS_PER_SOCKET 32
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#define ADP_SZ 64 /* hardware-provided max. */
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#define UV_CPUS_PER_AS 32 /* hardware-provided max. */
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#define ITEMS_PER_DESC 8
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/* the 'throttle' to prevent the hardware stay-busy bug */
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#define MAX_BAU_CONCURRENT 3
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#define UV_ACT_STATUS_MASK 0x3
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#define UV_ACT_STATUS_SIZE 2
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#define UV_DISTRIBUTION_SIZE 256
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#define UV_SW_ACK_NPENDING 8
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#define UV1_NET_ENDPOINT_INTD 0x38
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#define UV2_NET_ENDPOINT_INTD 0x28
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#define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
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UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
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#define UV_DESC_PSHIFT 49
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#define UV_PAYLOADQ_PNODE_SHIFT 49
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#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
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#define UV_BAU_BASENAME "sgi_uv/bau_tunables"
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#define UV_BAU_TUNABLES_DIR "sgi_uv"
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#define UV_BAU_TUNABLES_FILE "bau_tunables"
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#define WHITESPACE " \t\n"
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#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
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#define cpubit_isset(cpu, bau_local_cpumask) \
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test_bit((cpu), (bau_local_cpumask).bits)
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/* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */
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/*
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* UV2: Bit 19 selects between
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* (0): 10 microsecond timebase and
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* (1): 80 microseconds
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* we're using 655us, similar to UV1: 65 units of 10us
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*/
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#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
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#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
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#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
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UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
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UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
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#define BAU_MISC_CONTROL_MULT_MASK 3
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#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
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/* [30:28] URGENCY_7 an index into a table of times */
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#define BAU_URGENCY_7_SHIFT 28
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#define BAU_URGENCY_7_MASK 7
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#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
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/* [45:40] BAU - BAU transaction timeout select - a multiplier */
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#define BAU_TRANS_SHIFT 40
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#define BAU_TRANS_MASK 0x3f
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/*
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* shorten some awkward names
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*/
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#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
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#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
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#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
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#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
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#define write_gmmr uv_write_global_mmr64
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#define write_lmmr uv_write_local_mmr
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#define read_lmmr uv_read_local_mmr
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#define read_gmmr uv_read_global_mmr64
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/*
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* bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
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*/
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#define DS_IDLE 0
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#define DS_ACTIVE 1
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#define DS_DESTINATION_TIMEOUT 2
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#define DS_SOURCE_TIMEOUT 3
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/*
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* bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
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* values 1 and 3 will not occur
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* Decoded meaning ERROR BUSY AUX ERR
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* ------------------------------- ---- ----- -------
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* IDLE 0 0 0
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* BUSY (active) 0 1 0
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* SW Ack Timeout (destination) 1 0 0
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* SW Ack INTD rejected (strong NACK) 1 0 1
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* Source Side Time Out Detected 1 1 0
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* Destination Side PUT Failed 1 1 1
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*/
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#define UV2H_DESC_IDLE 0
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#define UV2H_DESC_BUSY 2
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#define UV2H_DESC_DEST_TIMEOUT 4
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#define UV2H_DESC_DEST_STRONG_NACK 5
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#define UV2H_DESC_SOURCE_TIMEOUT 6
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#define UV2H_DESC_DEST_PUT_ERR 7
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/*
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* delay for 'plugged' timeout retries, in microseconds
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*/
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#define PLUGGED_DELAY 10
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/*
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* threshholds at which to use IPI to free resources
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*/
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/* after this # consecutive 'plugged' timeouts, use IPI to release resources */
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#define PLUGSB4RESET 100
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/* after this many consecutive timeouts, use IPI to release resources */
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#define TIMEOUTSB4RESET 1
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/* at this number uses of IPI to release resources, giveup the request */
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#define IPI_RESET_LIMIT 1
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/* after this # consecutive successes, bump up the throttle if it was lowered */
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#define COMPLETE_THRESHOLD 5
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#define UV_LB_SUBNODEID 0x10
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/* these two are the same for UV1 and UV2: */
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#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
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#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
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/* 4 bits of software ack period */
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#define UV2_ACK_MASK 0x7UL
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#define UV2_ACK_UNITS_SHFT 3
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#define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
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#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
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/*
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* number of entries in the destination side payload queue
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*/
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#define DEST_Q_SIZE 20
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/*
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* number of destination side software ack resources
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*/
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#define DEST_NUM_RESOURCES 8
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/*
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* completion statuses for sending a TLB flush message
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*/
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#define FLUSH_RETRY_PLUGGED 1
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#define FLUSH_RETRY_TIMEOUT 2
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#define FLUSH_GIVEUP 3
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#define FLUSH_COMPLETE 4
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/*
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* tuning the action when the numalink network is extremely delayed
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*/
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#define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in
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microseconds */
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#define CONGESTED_REPS 10 /* long delays averaged over
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this many broadcasts */
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#define CONGESTED_PERIOD 30 /* time for the bau to be
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disabled, in seconds */
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/* see msg_type: */
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#define MSG_NOOP 0
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#define MSG_REGULAR 1
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#define MSG_RETRY 2
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/*
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* Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
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* If the 'multilevel' flag in the header portion of the descriptor
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* has been set to 0, then endpoint multi-unicast mode is selected.
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* The distribution specification (32 bytes) is interpreted as a 256-bit
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* distribution vector. Adjacent bits correspond to consecutive even numbered
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* nodeIDs. The result of adding the index of a given bit to the 15-bit
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* 'base_dest_nasid' field of the header corresponds to the
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* destination nodeID associated with that specified bit.
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*/
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struct pnmask {
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unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
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};
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/*
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* mask of cpu's on a uvhub
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* (during initialization we need to check that unsigned long has
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* enough bits for max. cpu's per uvhub)
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*/
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struct bau_local_cpumask {
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unsigned long bits;
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};
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/*
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* Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
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* only 12 bytes (96 bits) of the payload area are usable.
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* An additional 3 bytes (bits 27:4) of the header address are carried
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* to the next bytes of the destination payload queue.
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* And an additional 2 bytes of the header Suppl_A field are also
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* carried to the destination payload queue.
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* But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
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* of the destination payload queue, which is written by the hardware
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* with the s/w ack resource bit vector.
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* [ effective message contents (16 bytes (128 bits) maximum), not counting
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* the s/w ack bit vector ]
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*/
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/*
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* The payload is software-defined for INTD transactions
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*/
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struct bau_msg_payload {
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unsigned long address; /* signifies a page or all
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TLB's of the cpu */
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/* 64 bits */
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unsigned short sending_cpu; /* filled in by sender */
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/* 16 bits */
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unsigned short acknowledge_count; /* filled in by destination */
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/* 16 bits */
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unsigned int reserved1:32; /* not usable */
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};
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/*
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* Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
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* see table 4.2.3.0.1 in broacast_assist spec.
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*/
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struct bau_msg_header {
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unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
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/* bits 5:0 */
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unsigned int base_dest_nasid:15; /* nasid of the first bit */
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/* bits 20:6 */ /* in uvhub map */
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unsigned int command:8; /* message type */
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/* bits 28:21 */
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/* 0x38: SN3net EndPoint Message */
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unsigned int rsvd_1:3; /* must be zero */
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/* bits 31:29 */
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/* int will align on 32 bits */
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unsigned int rsvd_2:9; /* must be zero */
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/* bits 40:32 */
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/* Suppl_A is 56-41 */
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unsigned int sequence:16; /* message sequence number */
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/* bits 56:41 */ /* becomes bytes 16-17 of msg */
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/* Address field (96:57) is
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never used as an address
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(these are address bits
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42:3) */
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unsigned int rsvd_3:1; /* must be zero */
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/* bit 57 */
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/* address bits 27:4 are payload */
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/* these next 24 (58-81) bits become bytes 12-14 of msg */
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/* bits 65:58 land in byte 12 */
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unsigned int replied_to:1; /* sent as 0 by the source to
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byte 12 */
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/* bit 58 */
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unsigned int msg_type:3; /* software type of the
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message */
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/* bits 61:59 */
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unsigned int canceled:1; /* message canceled, resource
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is to be freed*/
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/* bit 62 */
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unsigned int payload_1a:1; /* not currently used */
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/* bit 63 */
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unsigned int payload_1b:2; /* not currently used */
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/* bits 65:64 */
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/* bits 73:66 land in byte 13 */
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unsigned int payload_1ca:6; /* not currently used */
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/* bits 71:66 */
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unsigned int payload_1c:2; /* not currently used */
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/* bits 73:72 */
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/* bits 81:74 land in byte 14 */
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unsigned int payload_1d:6; /* not currently used */
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/* bits 79:74 */
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unsigned int payload_1e:2; /* not currently used */
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/* bits 81:80 */
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unsigned int rsvd_4:7; /* must be zero */
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/* bits 88:82 */
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unsigned int swack_flag:1; /* software acknowledge flag */
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/* bit 89 */
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/* INTD trasactions at
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destination are to wait for
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software acknowledge */
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unsigned int rsvd_5:6; /* must be zero */
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/* bits 95:90 */
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unsigned int rsvd_6:5; /* must be zero */
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/* bits 100:96 */
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unsigned int int_both:1; /* if 1, interrupt both sockets
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on the uvhub */
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/* bit 101*/
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unsigned int fairness:3; /* usually zero */
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/* bits 104:102 */
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unsigned int multilevel:1; /* multi-level multicast
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format */
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/* bit 105 */
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/* 0 for TLB: endpoint multi-unicast messages */
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unsigned int chaining:1; /* next descriptor is part of
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this activation*/
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/* bit 106 */
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unsigned int rsvd_7:21; /* must be zero */
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/* bits 127:107 */
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};
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/*
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* The activation descriptor:
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* The format of the message to send, plus all accompanying control
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* Should be 64 bytes
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*/
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struct bau_desc {
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struct pnmask distribution;
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/*
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* message template, consisting of header and payload:
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*/
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struct bau_msg_header header;
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struct bau_msg_payload payload;
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};
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/*
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* -payload-- ---------header------
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* bytes 0-11 bits 41-56 bits 58-81
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* A B (2) C (3)
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*
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* A/B/C are moved to:
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* A C B
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* bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
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* ------------payload queue-----------
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*/
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/*
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* The payload queue on the destination side is an array of these.
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* With BAU_MISC_CONTROL set for software acknowledge mode, the messages
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* are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
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* bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
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* (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
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* swack_vec and payload_2)
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* "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
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* Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
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* operation."
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*/
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struct bau_pq_entry {
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unsigned long address; /* signifies a page or all TLB's
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of the cpu */
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/* 64 bits, bytes 0-7 */
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unsigned short sending_cpu; /* cpu that sent the message */
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/* 16 bits, bytes 8-9 */
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unsigned short acknowledge_count; /* filled in by destination */
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/* 16 bits, bytes 10-11 */
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/* these next 3 bytes come from bits 58-81 of the message header */
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unsigned short replied_to:1; /* sent as 0 by the source */
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unsigned short msg_type:3; /* software message type */
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unsigned short canceled:1; /* sent as 0 by the source */
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unsigned short unused1:3; /* not currently using */
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/* byte 12 */
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unsigned char unused2a; /* not currently using */
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/* byte 13 */
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unsigned char unused2; /* not currently using */
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/* byte 14 */
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unsigned char swack_vec; /* filled in by the hardware */
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/* byte 15 (bits 127:120) */
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unsigned short sequence; /* message sequence number */
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/* bytes 16-17 */
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unsigned char unused4[2]; /* not currently using bytes 18-19 */
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/* bytes 18-19 */
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int number_of_cpus; /* filled in at destination */
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/* 32 bits, bytes 20-23 (aligned) */
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unsigned char unused5[8]; /* not using */
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/* bytes 24-31 */
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};
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struct msg_desc {
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struct bau_pq_entry *msg;
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int msg_slot;
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int swack_slot;
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struct bau_pq_entry *queue_first;
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struct bau_pq_entry *queue_last;
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};
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struct reset_args {
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int sender;
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};
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/*
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* This structure is allocated per_cpu for UV TLB shootdown statistics.
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*/
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struct ptc_stats {
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/* sender statistics */
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unsigned long s_giveup; /* number of fall backs to
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IPI-style flushes */
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unsigned long s_requestor; /* number of shootdown
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requests */
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unsigned long s_stimeout; /* source side timeouts */
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unsigned long s_dtimeout; /* destination side timeouts */
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unsigned long s_time; /* time spent in sending side */
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unsigned long s_retriesok; /* successful retries */
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unsigned long s_ntargcpu; /* total number of cpu's
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targeted */
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unsigned long s_ntargself; /* times the sending cpu was
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targeted */
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unsigned long s_ntarglocals; /* targets of cpus on the local
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blade */
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unsigned long s_ntargremotes; /* targets of cpus on remote
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blades */
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unsigned long s_ntarglocaluvhub; /* targets of the local hub */
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unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
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unsigned long s_ntarguvhub; /* total number of uvhubs
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targeted */
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unsigned long s_ntarguvhub16; /* number of times target
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hubs >= 16*/
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unsigned long s_ntarguvhub8; /* number of times target
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hubs >= 8 */
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unsigned long s_ntarguvhub4; /* number of times target
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hubs >= 4 */
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unsigned long s_ntarguvhub2; /* number of times target
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hubs >= 2 */
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unsigned long s_ntarguvhub1; /* number of times target
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hubs == 1 */
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unsigned long s_resets_plug; /* ipi-style resets from plug
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state */
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unsigned long s_resets_timeout; /* ipi-style resets from
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timeouts */
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unsigned long s_busy; /* status stayed busy past
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s/w timer */
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unsigned long s_throttles; /* waits in throttle */
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unsigned long s_retry_messages; /* retry broadcasts */
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unsigned long s_bau_reenabled; /* for bau enable/disable */
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unsigned long s_bau_disabled; /* for bau enable/disable */
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/* destination statistics */
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unsigned long d_alltlb; /* times all tlb's on this
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cpu were flushed */
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unsigned long d_onetlb; /* times just one tlb on this
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cpu was flushed */
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unsigned long d_multmsg; /* interrupts with multiple
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messages */
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unsigned long d_nomsg; /* interrupts with no message */
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unsigned long d_time; /* time spent on destination
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side */
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unsigned long d_requestee; /* number of messages
|
|
processed */
|
|
unsigned long d_retries; /* number of retry messages
|
|
processed */
|
|
unsigned long d_canceled; /* number of messages canceled
|
|
by retries */
|
|
unsigned long d_nocanceled; /* retries that found nothing
|
|
to cancel */
|
|
unsigned long d_resets; /* number of ipi-style requests
|
|
processed */
|
|
unsigned long d_rcanceled; /* number of messages canceled
|
|
by resets */
|
|
};
|
|
|
|
struct tunables {
|
|
int *tunp;
|
|
int deflt;
|
|
};
|
|
|
|
struct hub_and_pnode {
|
|
short uvhub;
|
|
short pnode;
|
|
};
|
|
|
|
struct socket_desc {
|
|
short num_cpus;
|
|
short cpu_number[MAX_CPUS_PER_SOCKET];
|
|
};
|
|
|
|
struct uvhub_desc {
|
|
unsigned short socket_mask;
|
|
short num_cpus;
|
|
short uvhub;
|
|
short pnode;
|
|
struct socket_desc socket[2];
|
|
};
|
|
|
|
/*
|
|
* one per-cpu; to locate the software tables
|
|
*/
|
|
struct bau_control {
|
|
struct bau_desc *descriptor_base;
|
|
struct bau_pq_entry *queue_first;
|
|
struct bau_pq_entry *queue_last;
|
|
struct bau_pq_entry *bau_msg_head;
|
|
struct bau_control *uvhub_master;
|
|
struct bau_control *socket_master;
|
|
struct ptc_stats *statp;
|
|
cpumask_t *cpumask;
|
|
unsigned long timeout_interval;
|
|
unsigned long set_bau_on_time;
|
|
atomic_t active_descriptor_count;
|
|
int plugged_tries;
|
|
int timeout_tries;
|
|
int ipi_attempts;
|
|
int conseccompletes;
|
|
int baudisabled;
|
|
int set_bau_off;
|
|
short cpu;
|
|
short osnode;
|
|
short uvhub_cpu;
|
|
short uvhub;
|
|
short cpus_in_socket;
|
|
short cpus_in_uvhub;
|
|
short partition_base_pnode;
|
|
unsigned short message_number;
|
|
unsigned short uvhub_quiesce;
|
|
short socket_acknowledge_count[DEST_Q_SIZE];
|
|
cycles_t send_message;
|
|
spinlock_t uvhub_lock;
|
|
spinlock_t queue_lock;
|
|
/* tunables */
|
|
int max_concurr;
|
|
int max_concurr_const;
|
|
int plugged_delay;
|
|
int plugsb4reset;
|
|
int timeoutsb4reset;
|
|
int ipi_reset_limit;
|
|
int complete_threshold;
|
|
int cong_response_us;
|
|
int cong_reps;
|
|
int cong_period;
|
|
cycles_t period_time;
|
|
long period_requests;
|
|
struct hub_and_pnode *thp;
|
|
};
|
|
|
|
static inline unsigned long read_mmr_uv2_status(void)
|
|
{
|
|
return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
|
|
}
|
|
|
|
static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
|
|
{
|
|
write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
|
|
}
|
|
|
|
static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
|
|
{
|
|
write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
|
|
}
|
|
|
|
static inline void write_mmr_activation(unsigned long index)
|
|
{
|
|
write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
|
|
}
|
|
|
|
static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
|
|
{
|
|
write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
|
|
}
|
|
|
|
static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
|
|
{
|
|
write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
|
|
}
|
|
|
|
static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
|
|
{
|
|
write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
|
|
}
|
|
|
|
static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
|
|
{
|
|
write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
|
|
}
|
|
|
|
static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
|
|
{
|
|
write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
|
|
}
|
|
|
|
static inline unsigned long read_mmr_misc_control(int pnode)
|
|
{
|
|
return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
|
|
}
|
|
|
|
static inline void write_mmr_sw_ack(unsigned long mr)
|
|
{
|
|
uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
|
|
}
|
|
|
|
static inline unsigned long read_mmr_sw_ack(void)
|
|
{
|
|
return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
|
|
}
|
|
|
|
static inline unsigned long read_gmmr_sw_ack(int pnode)
|
|
{
|
|
return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
|
|
}
|
|
|
|
static inline void write_mmr_data_config(int pnode, unsigned long mr)
|
|
{
|
|
uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
|
|
}
|
|
|
|
static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
|
|
{
|
|
return constant_test_bit(uvhub, &dstp->bits[0]);
|
|
}
|
|
static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
|
|
{
|
|
__set_bit(pnode, &dstp->bits[0]);
|
|
}
|
|
static inline void bau_uvhubs_clear(struct pnmask *dstp,
|
|
int nbits)
|
|
{
|
|
bitmap_zero(&dstp->bits[0], nbits);
|
|
}
|
|
static inline int bau_uvhub_weight(struct pnmask *dstp)
|
|
{
|
|
return bitmap_weight((unsigned long *)&dstp->bits[0],
|
|
UV_DISTRIBUTION_SIZE);
|
|
}
|
|
|
|
static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
|
|
{
|
|
bitmap_zero(&dstp->bits, nbits);
|
|
}
|
|
|
|
extern void uv_bau_message_intr1(void);
|
|
extern void uv_bau_timeout_intr1(void);
|
|
|
|
struct atomic_short {
|
|
short counter;
|
|
};
|
|
|
|
/*
|
|
* atomic_read_short - read a short atomic variable
|
|
* @v: pointer of type atomic_short
|
|
*
|
|
* Atomically reads the value of @v.
|
|
*/
|
|
static inline int atomic_read_short(const struct atomic_short *v)
|
|
{
|
|
return v->counter;
|
|
}
|
|
|
|
/*
|
|
* atom_asr - add and return a short int
|
|
* @i: short value to add
|
|
* @v: pointer of type atomic_short
|
|
*
|
|
* Atomically adds @i to @v and returns @i + @v
|
|
*/
|
|
static inline int atom_asr(short i, struct atomic_short *v)
|
|
{
|
|
short __i = i;
|
|
asm volatile(LOCK_PREFIX "xaddw %0, %1"
|
|
: "+r" (i), "+m" (v->counter)
|
|
: : "memory");
|
|
return i + __i;
|
|
}
|
|
|
|
/*
|
|
* conditionally add 1 to *v, unless *v is >= u
|
|
* return 0 if we cannot add 1 to *v because it is >= u
|
|
* return 1 if we can add 1 to *v because it is < u
|
|
* the add is atomic
|
|
*
|
|
* This is close to atomic_add_unless(), but this allows the 'u' value
|
|
* to be lowered below the current 'v'. atomic_add_unless can only stop
|
|
* on equal.
|
|
*/
|
|
static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
|
|
{
|
|
spin_lock(lock);
|
|
if (atomic_read(v) >= u) {
|
|
spin_unlock(lock);
|
|
return 0;
|
|
}
|
|
atomic_inc(v);
|
|
spin_unlock(lock);
|
|
return 1;
|
|
}
|
|
|
|
#endif /* _ASM_X86_UV_UV_BAU_H */
|