![Paulo Zanoni](/assets/img/avatar_default.png)
Because we're currently using FBC_UNSUPPORTED_MODE for two different cases. This commit will also allow us to write the next one without hiding information from the user. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
742 lines
21 KiB
C
742 lines
21 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/**
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* DOC: Frame Buffer Compression (FBC)
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*
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* FBC tries to save memory bandwidth (and so power consumption) by
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* compressing the amount of memory used by the display. It is total
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* transparent to user space and completely handled in the kernel.
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*
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* The benefits of FBC are mostly visible with solid backgrounds and
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* variation-less patterns. It comes from keeping the memory footprint small
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* and having fewer memory pages opened and accessed for refreshing the display.
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*
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* i915 is responsible to reserve stolen memory for FBC and configure its
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* offset on proper registers. The hardware takes care of all
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* compress/decompress. However there are many known cases where we have to
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* forcibly disable it to allow proper screen updates.
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*/
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#include "intel_drv.h"
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#include "i915_drv.h"
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static void i8xx_fbc_disable(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 fbc_ctl;
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dev_priv->fbc.enabled = false;
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/* Disable compression */
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fbc_ctl = I915_READ(FBC_CONTROL);
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if ((fbc_ctl & FBC_CTL_EN) == 0)
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return;
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fbc_ctl &= ~FBC_CTL_EN;
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I915_WRITE(FBC_CONTROL, fbc_ctl);
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/* Wait for compressing bit to clear */
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if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
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DRM_DEBUG_KMS("FBC idle timed out\n");
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return;
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}
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DRM_DEBUG_KMS("disabled FBC\n");
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}
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static void i8xx_fbc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_framebuffer *fb = crtc->primary->fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int cfb_pitch;
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int i;
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u32 fbc_ctl;
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dev_priv->fbc.enabled = true;
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/* Note: fbc.threshold == 1 for i8xx */
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cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE;
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if (fb->pitches[0] < cfb_pitch)
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cfb_pitch = fb->pitches[0];
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/* FBC_CTL wants 32B or 64B units */
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if (IS_GEN2(dev))
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cfb_pitch = (cfb_pitch / 32) - 1;
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else
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cfb_pitch = (cfb_pitch / 64) - 1;
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/* Clear old tags */
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for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
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I915_WRITE(FBC_TAG + (i * 4), 0);
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if (IS_GEN4(dev)) {
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u32 fbc_ctl2;
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/* Set it up... */
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fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
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fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
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I915_WRITE(FBC_CONTROL2, fbc_ctl2);
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I915_WRITE(FBC_FENCE_OFF, crtc->y);
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}
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/* enable it... */
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fbc_ctl = I915_READ(FBC_CONTROL);
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fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
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fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
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if (IS_I945GM(dev))
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fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
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fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
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fbc_ctl |= obj->fence_reg;
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I915_WRITE(FBC_CONTROL, fbc_ctl);
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DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
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cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
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}
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static bool i8xx_fbc_enabled(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
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}
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static void g4x_fbc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_framebuffer *fb = crtc->primary->fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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u32 dpfc_ctl;
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dev_priv->fbc.enabled = true;
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dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
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if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
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dpfc_ctl |= DPFC_CTL_LIMIT_2X;
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else
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dpfc_ctl |= DPFC_CTL_LIMIT_1X;
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dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
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I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
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/* enable it... */
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I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
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DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
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}
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static void g4x_fbc_disable(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 dpfc_ctl;
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dev_priv->fbc.enabled = false;
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/* Disable compression */
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dpfc_ctl = I915_READ(DPFC_CONTROL);
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if (dpfc_ctl & DPFC_CTL_EN) {
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dpfc_ctl &= ~DPFC_CTL_EN;
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I915_WRITE(DPFC_CONTROL, dpfc_ctl);
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DRM_DEBUG_KMS("disabled FBC\n");
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}
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}
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static bool g4x_fbc_enabled(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
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}
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static void intel_fbc_nuke(struct drm_i915_private *dev_priv)
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{
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I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
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POSTING_READ(MSG_FBC_REND_STATE);
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}
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static void ilk_fbc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_framebuffer *fb = crtc->primary->fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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u32 dpfc_ctl;
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dev_priv->fbc.enabled = true;
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dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
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if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
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dev_priv->fbc.threshold++;
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switch (dev_priv->fbc.threshold) {
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case 4:
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case 3:
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dpfc_ctl |= DPFC_CTL_LIMIT_4X;
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break;
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case 2:
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dpfc_ctl |= DPFC_CTL_LIMIT_2X;
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break;
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case 1:
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dpfc_ctl |= DPFC_CTL_LIMIT_1X;
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break;
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}
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dpfc_ctl |= DPFC_CTL_FENCE_EN;
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if (IS_GEN5(dev))
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dpfc_ctl |= obj->fence_reg;
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I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
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I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
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/* enable it... */
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I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
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if (IS_GEN6(dev)) {
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I915_WRITE(SNB_DPFC_CTL_SA,
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SNB_CPU_FENCE_ENABLE | obj->fence_reg);
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I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
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}
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intel_fbc_nuke(dev_priv);
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DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
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}
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static void ilk_fbc_disable(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 dpfc_ctl;
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dev_priv->fbc.enabled = false;
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/* Disable compression */
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dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
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if (dpfc_ctl & DPFC_CTL_EN) {
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dpfc_ctl &= ~DPFC_CTL_EN;
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I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
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DRM_DEBUG_KMS("disabled FBC\n");
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}
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}
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static bool ilk_fbc_enabled(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
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}
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static void gen7_fbc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_framebuffer *fb = crtc->primary->fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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u32 dpfc_ctl;
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dev_priv->fbc.enabled = true;
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dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
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if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
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dev_priv->fbc.threshold++;
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switch (dev_priv->fbc.threshold) {
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case 4:
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case 3:
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dpfc_ctl |= DPFC_CTL_LIMIT_4X;
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break;
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case 2:
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dpfc_ctl |= DPFC_CTL_LIMIT_2X;
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break;
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case 1:
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dpfc_ctl |= DPFC_CTL_LIMIT_1X;
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break;
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}
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dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
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if (dev_priv->fbc.false_color)
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dpfc_ctl |= FBC_CTL_FALSE_COLOR;
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I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
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if (IS_IVYBRIDGE(dev)) {
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/* WaFbcAsynchFlipDisableFbcQueue:ivb */
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I915_WRITE(ILK_DISPLAY_CHICKEN1,
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I915_READ(ILK_DISPLAY_CHICKEN1) |
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ILK_FBCQ_DIS);
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} else {
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/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
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I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
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I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
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HSW_FBCQ_DIS);
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}
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I915_WRITE(SNB_DPFC_CTL_SA,
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SNB_CPU_FENCE_ENABLE | obj->fence_reg);
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I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
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intel_fbc_nuke(dev_priv);
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DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
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}
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/**
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* intel_fbc_enabled - Is FBC enabled?
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* @dev: the drm_device
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*
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* This function is used to verify the current state of FBC.
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* FIXME: This should be tracked in the plane config eventually
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* instead of queried at runtime for most callers.
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*/
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bool intel_fbc_enabled(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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return dev_priv->fbc.enabled;
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}
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static void intel_fbc_work_fn(struct work_struct *__work)
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{
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struct intel_fbc_work *work =
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container_of(to_delayed_work(__work),
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struct intel_fbc_work, work);
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struct drm_device *dev = work->crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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mutex_lock(&dev->struct_mutex);
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if (work == dev_priv->fbc.fbc_work) {
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/* Double check that we haven't switched fb without cancelling
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* the prior work.
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*/
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if (work->crtc->primary->fb == work->fb) {
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dev_priv->display.enable_fbc(work->crtc);
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dev_priv->fbc.crtc = to_intel_crtc(work->crtc);
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dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
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dev_priv->fbc.y = work->crtc->y;
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}
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dev_priv->fbc.fbc_work = NULL;
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}
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mutex_unlock(&dev->struct_mutex);
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kfree(work);
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}
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static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv)
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{
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if (dev_priv->fbc.fbc_work == NULL)
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return;
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DRM_DEBUG_KMS("cancelling pending FBC enable\n");
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/* Synchronisation is provided by struct_mutex and checking of
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* dev_priv->fbc.fbc_work, so we can perform the cancellation
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* entirely asynchronously.
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*/
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if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
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/* tasklet was killed before being run, clean up */
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kfree(dev_priv->fbc.fbc_work);
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/* Mark the work as no longer wanted so that if it does
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* wake-up (because the work was already running and waiting
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* for our mutex), it will discover that is no longer
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* necessary to run.
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*/
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dev_priv->fbc.fbc_work = NULL;
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}
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static void intel_fbc_enable(struct drm_crtc *crtc)
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{
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struct intel_fbc_work *work;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (!dev_priv->display.enable_fbc)
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return;
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intel_fbc_cancel_work(dev_priv);
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work = kzalloc(sizeof(*work), GFP_KERNEL);
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if (work == NULL) {
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DRM_ERROR("Failed to allocate FBC work structure\n");
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dev_priv->display.enable_fbc(crtc);
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return;
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}
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work->crtc = crtc;
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work->fb = crtc->primary->fb;
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INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
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dev_priv->fbc.fbc_work = work;
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/* Delay the actual enabling to let pageflipping cease and the
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* display to settle before starting the compression. Note that
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* this delay also serves a second purpose: it allows for a
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* vblank to pass after disabling the FBC before we attempt
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* to modify the control registers.
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*
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* A more complicated solution would involve tracking vblanks
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* following the termination of the page-flipping sequence
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* and indeed performing the enable as a co-routine and not
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* waiting synchronously upon the vblank.
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*
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* WaFbcWaitForVBlankBeforeEnable:ilk,snb
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*/
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schedule_delayed_work(&work->work, msecs_to_jiffies(50));
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}
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/**
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* intel_fbc_disable - disable FBC
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* @dev: the drm_device
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*
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* This function disables FBC.
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*/
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void intel_fbc_disable(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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intel_fbc_cancel_work(dev_priv);
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if (!dev_priv->display.disable_fbc)
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return;
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dev_priv->display.disable_fbc(dev);
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dev_priv->fbc.crtc = NULL;
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}
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static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
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enum no_fbc_reason reason)
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{
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if (dev_priv->fbc.no_fbc_reason == reason)
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return false;
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dev_priv->fbc.no_fbc_reason = reason;
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return true;
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}
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static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv)
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{
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struct drm_crtc *crtc = NULL, *tmp_crtc;
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enum pipe pipe;
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bool pipe_a_only = false, one_pipe_only = false;
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if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
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pipe_a_only = true;
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else if (INTEL_INFO(dev_priv)->gen <= 4)
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one_pipe_only = true;
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for_each_pipe(dev_priv, pipe) {
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tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
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if (intel_crtc_active(tmp_crtc) &&
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to_intel_plane_state(tmp_crtc->primary->state)->visible) {
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if (one_pipe_only && crtc) {
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if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
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DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
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return NULL;
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}
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crtc = tmp_crtc;
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}
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|
|
if (pipe_a_only)
|
|
break;
|
|
}
|
|
|
|
if (!crtc || crtc->primary->fb == NULL) {
|
|
if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
|
|
DRM_DEBUG_KMS("no output, disabling\n");
|
|
return NULL;
|
|
}
|
|
|
|
return crtc;
|
|
}
|
|
|
|
/**
|
|
* intel_fbc_update - enable/disable FBC as needed
|
|
* @dev: the drm_device
|
|
*
|
|
* Set up the framebuffer compression hardware at mode set time. We
|
|
* enable it if possible:
|
|
* - plane A only (on pre-965)
|
|
* - no pixel mulitply/line duplication
|
|
* - no alpha buffer discard
|
|
* - no dual wide
|
|
* - framebuffer <= max_hdisplay in width, max_vdisplay in height
|
|
*
|
|
* We can't assume that any compression will take place (worst case),
|
|
* so the compressed buffer has to be the same size as the uncompressed
|
|
* one. It also must reside (along with the line length buffer) in
|
|
* stolen memory.
|
|
*
|
|
* We need to enable/disable FBC on a global basis.
|
|
*/
|
|
void intel_fbc_update(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_crtc *crtc = NULL;
|
|
struct intel_crtc *intel_crtc;
|
|
struct drm_framebuffer *fb;
|
|
struct drm_i915_gem_object *obj;
|
|
const struct drm_display_mode *adjusted_mode;
|
|
unsigned int max_width, max_height;
|
|
|
|
if (!HAS_FBC(dev))
|
|
return;
|
|
|
|
/* disable framebuffer compression in vGPU */
|
|
if (intel_vgpu_active(dev))
|
|
i915.enable_fbc = 0;
|
|
|
|
if (i915.enable_fbc < 0) {
|
|
if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
|
|
DRM_DEBUG_KMS("disabled per chip default\n");
|
|
goto out_disable;
|
|
}
|
|
|
|
if (!i915.enable_fbc) {
|
|
if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
|
|
DRM_DEBUG_KMS("fbc disabled per module param\n");
|
|
goto out_disable;
|
|
}
|
|
|
|
/*
|
|
* If FBC is already on, we just have to verify that we can
|
|
* keep it that way...
|
|
* Need to disable if:
|
|
* - more than one pipe is active
|
|
* - changing FBC params (stride, fence, mode)
|
|
* - new fb is too large to fit in compressed buffer
|
|
* - going to an unsupported config (interlace, pixel multiply, etc.)
|
|
*/
|
|
crtc = intel_fbc_find_crtc(dev_priv);
|
|
if (!crtc)
|
|
goto out_disable;
|
|
|
|
intel_crtc = to_intel_crtc(crtc);
|
|
fb = crtc->primary->fb;
|
|
obj = intel_fb_obj(fb);
|
|
adjusted_mode = &intel_crtc->config->base.adjusted_mode;
|
|
|
|
if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
|
|
(adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
|
|
if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
|
|
DRM_DEBUG_KMS("mode incompatible with compression, "
|
|
"disabling\n");
|
|
goto out_disable;
|
|
}
|
|
|
|
if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
|
|
max_width = 4096;
|
|
max_height = 4096;
|
|
} else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
|
|
max_width = 4096;
|
|
max_height = 2048;
|
|
} else {
|
|
max_width = 2048;
|
|
max_height = 1536;
|
|
}
|
|
if (intel_crtc->config->pipe_src_w > max_width ||
|
|
intel_crtc->config->pipe_src_h > max_height) {
|
|
if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
|
|
DRM_DEBUG_KMS("mode too large for compression, disabling\n");
|
|
goto out_disable;
|
|
}
|
|
if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
|
|
intel_crtc->plane != PLANE_A) {
|
|
if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
|
|
DRM_DEBUG_KMS("plane not A, disabling compression\n");
|
|
goto out_disable;
|
|
}
|
|
|
|
/* The use of a CPU fence is mandatory in order to detect writes
|
|
* by the CPU to the scanout and trigger updates to the FBC.
|
|
*/
|
|
if (obj->tiling_mode != I915_TILING_X ||
|
|
obj->fence_reg == I915_FENCE_REG_NONE) {
|
|
if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
|
|
DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
|
|
goto out_disable;
|
|
}
|
|
if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
|
|
crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) {
|
|
if (set_no_fbc_reason(dev_priv, FBC_ROTATION))
|
|
DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
|
|
goto out_disable;
|
|
}
|
|
|
|
/* If the kernel debugger is active, always disable compression */
|
|
if (in_dbg_master())
|
|
goto out_disable;
|
|
|
|
if (i915_gem_stolen_setup_compression(dev, obj->base.size,
|
|
drm_format_plane_cpp(fb->pixel_format, 0))) {
|
|
if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
|
|
DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
|
|
goto out_disable;
|
|
}
|
|
|
|
/* If the scanout has not changed, don't modify the FBC settings.
|
|
* Note that we make the fundamental assumption that the fb->obj
|
|
* cannot be unpinned (and have its GTT offset and fence revoked)
|
|
* without first being decoupled from the scanout and FBC disabled.
|
|
*/
|
|
if (dev_priv->fbc.crtc == intel_crtc &&
|
|
dev_priv->fbc.fb_id == fb->base.id &&
|
|
dev_priv->fbc.y == crtc->y)
|
|
return;
|
|
|
|
if (intel_fbc_enabled(dev)) {
|
|
/* We update FBC along two paths, after changing fb/crtc
|
|
* configuration (modeswitching) and after page-flipping
|
|
* finishes. For the latter, we know that not only did
|
|
* we disable the FBC at the start of the page-flip
|
|
* sequence, but also more than one vblank has passed.
|
|
*
|
|
* For the former case of modeswitching, it is possible
|
|
* to switch between two FBC valid configurations
|
|
* instantaneously so we do need to disable the FBC
|
|
* before we can modify its control registers. We also
|
|
* have to wait for the next vblank for that to take
|
|
* effect. However, since we delay enabling FBC we can
|
|
* assume that a vblank has passed since disabling and
|
|
* that we can safely alter the registers in the deferred
|
|
* callback.
|
|
*
|
|
* In the scenario that we go from a valid to invalid
|
|
* and then back to valid FBC configuration we have
|
|
* no strict enforcement that a vblank occurred since
|
|
* disabling the FBC. However, along all current pipe
|
|
* disabling paths we do need to wait for a vblank at
|
|
* some point. And we wait before enabling FBC anyway.
|
|
*/
|
|
DRM_DEBUG_KMS("disabling active FBC for update\n");
|
|
intel_fbc_disable(dev);
|
|
}
|
|
|
|
intel_fbc_enable(crtc);
|
|
dev_priv->fbc.no_fbc_reason = FBC_OK;
|
|
return;
|
|
|
|
out_disable:
|
|
/* Multiple disables should be harmless */
|
|
if (intel_fbc_enabled(dev)) {
|
|
DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
|
|
intel_fbc_disable(dev);
|
|
}
|
|
i915_gem_stolen_cleanup_compression(dev);
|
|
}
|
|
|
|
void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
|
|
unsigned int frontbuffer_bits,
|
|
enum fb_op_origin origin)
|
|
{
|
|
struct drm_device *dev = dev_priv->dev;
|
|
unsigned int fbc_bits;
|
|
|
|
if (origin == ORIGIN_GTT)
|
|
return;
|
|
|
|
if (dev_priv->fbc.enabled)
|
|
fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe);
|
|
else if (dev_priv->fbc.fbc_work)
|
|
fbc_bits = INTEL_FRONTBUFFER_PRIMARY(
|
|
to_intel_crtc(dev_priv->fbc.fbc_work->crtc)->pipe);
|
|
else
|
|
fbc_bits = dev_priv->fbc.possible_framebuffer_bits;
|
|
|
|
dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits);
|
|
|
|
if (dev_priv->fbc.busy_bits)
|
|
intel_fbc_disable(dev);
|
|
}
|
|
|
|
void intel_fbc_flush(struct drm_i915_private *dev_priv,
|
|
unsigned int frontbuffer_bits)
|
|
{
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
if (!dev_priv->fbc.busy_bits)
|
|
return;
|
|
|
|
dev_priv->fbc.busy_bits &= ~frontbuffer_bits;
|
|
|
|
if (!dev_priv->fbc.busy_bits)
|
|
intel_fbc_update(dev);
|
|
}
|
|
|
|
/**
|
|
* intel_fbc_init - Initialize FBC
|
|
* @dev_priv: the i915 device
|
|
*
|
|
* This function might be called during PM init process.
|
|
*/
|
|
void intel_fbc_init(struct drm_i915_private *dev_priv)
|
|
{
|
|
enum pipe pipe;
|
|
|
|
if (!HAS_FBC(dev_priv)) {
|
|
dev_priv->fbc.enabled = false;
|
|
dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED;
|
|
return;
|
|
}
|
|
|
|
for_each_pipe(dev_priv, pipe) {
|
|
dev_priv->fbc.possible_framebuffer_bits |=
|
|
INTEL_FRONTBUFFER_PRIMARY(pipe);
|
|
|
|
if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
|
|
break;
|
|
}
|
|
|
|
if (INTEL_INFO(dev_priv)->gen >= 7) {
|
|
dev_priv->display.fbc_enabled = ilk_fbc_enabled;
|
|
dev_priv->display.enable_fbc = gen7_fbc_enable;
|
|
dev_priv->display.disable_fbc = ilk_fbc_disable;
|
|
} else if (INTEL_INFO(dev_priv)->gen >= 5) {
|
|
dev_priv->display.fbc_enabled = ilk_fbc_enabled;
|
|
dev_priv->display.enable_fbc = ilk_fbc_enable;
|
|
dev_priv->display.disable_fbc = ilk_fbc_disable;
|
|
} else if (IS_GM45(dev_priv)) {
|
|
dev_priv->display.fbc_enabled = g4x_fbc_enabled;
|
|
dev_priv->display.enable_fbc = g4x_fbc_enable;
|
|
dev_priv->display.disable_fbc = g4x_fbc_disable;
|
|
} else {
|
|
dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
|
|
dev_priv->display.enable_fbc = i8xx_fbc_enable;
|
|
dev_priv->display.disable_fbc = i8xx_fbc_disable;
|
|
|
|
/* This value was pulled out of someone's hat */
|
|
I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
|
|
}
|
|
|
|
dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev);
|
|
}
|