![Palmer Dabbelt](/assets/img/avatar_default.png)
Multiple architectures define this as a trivial function, and I'm adding another one as part of the RISC-V port. Add a __weak version of pcibios_align_resource() and delete the now-obselete ones in a handful of ports. The only functional change should be that a handful of ports used to export pcibios_fixup_bus(). Only some architectures export this, so I just dropped it. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
604 lines
15 KiB
C
604 lines
15 KiB
C
/*
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* pci.c - Low-Level PCI Access in IA-64
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*
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* Derived from bios32.c of i386 tree.
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*
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* (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Bjorn Helgaas <bjorn.helgaas@hp.com>
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* Copyright (C) 2004 Silicon Graphics, Inc.
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*
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* Note: Above list of copyright holders is incomplete...
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*/
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#include <linux/acpi.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/bootmem.h>
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#include <linux/export.h>
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#include <asm/machvec.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/sal.h>
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#include <asm/smp.h>
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#include <asm/irq.h>
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#include <asm/hw_irq.h>
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/*
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* Low-level SAL-based PCI configuration access functions. Note that SAL
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* calls are already serialized (via sal_lock), so we don't need another
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* synchronization mechanism here.
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*/
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#define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
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(((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
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/* SAL 3.2 adds support for extended config space. */
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#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
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(((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
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int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 *value)
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{
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u64 addr, data = 0;
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int mode, result;
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if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
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return -EINVAL;
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if ((seg | reg) <= 255) {
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addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
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mode = 0;
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} else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
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addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
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mode = 1;
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} else {
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return -EINVAL;
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}
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result = ia64_sal_pci_config_read(addr, mode, len, &data);
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if (result != 0)
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return -EINVAL;
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*value = (u32) data;
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return 0;
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}
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int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 value)
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{
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u64 addr;
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int mode, result;
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if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
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return -EINVAL;
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if ((seg | reg) <= 255) {
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addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
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mode = 0;
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} else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
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addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
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mode = 1;
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} else {
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return -EINVAL;
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}
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result = ia64_sal_pci_config_write(addr, mode, len, value);
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if (result != 0)
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return -EINVAL;
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return 0;
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}
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static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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return raw_pci_read(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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}
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static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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return raw_pci_write(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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}
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struct pci_ops pci_root_ops = {
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.read = pci_read,
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.write = pci_write,
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};
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struct pci_root_info {
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struct acpi_pci_root_info common;
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struct pci_controller controller;
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struct list_head io_resources;
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};
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static unsigned int new_space(u64 phys_base, int sparse)
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{
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u64 mmio_base;
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int i;
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if (phys_base == 0)
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return 0; /* legacy I/O port space */
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mmio_base = (u64) ioremap(phys_base, 0);
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for (i = 0; i < num_io_spaces; i++)
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if (io_space[i].mmio_base == mmio_base &&
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io_space[i].sparse == sparse)
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return i;
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if (num_io_spaces == MAX_IO_SPACES) {
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pr_err("PCI: Too many IO port spaces "
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"(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
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return ~0;
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}
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i = num_io_spaces++;
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io_space[i].mmio_base = mmio_base;
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io_space[i].sparse = sparse;
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return i;
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}
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static int add_io_space(struct device *dev, struct pci_root_info *info,
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struct resource_entry *entry)
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{
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struct resource_entry *iospace;
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struct resource *resource, *res = entry->res;
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char *name;
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unsigned long base, min, max, base_port;
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unsigned int sparse = 0, space_nr, len;
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len = strlen(info->common.name) + 32;
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iospace = resource_list_create_entry(NULL, len);
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if (!iospace) {
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dev_err(dev, "PCI: No memory for %s I/O port space\n",
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info->common.name);
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return -ENOMEM;
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}
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if (res->flags & IORESOURCE_IO_SPARSE)
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sparse = 1;
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space_nr = new_space(entry->offset, sparse);
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if (space_nr == ~0)
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goto free_resource;
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name = (char *)(iospace + 1);
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min = res->start - entry->offset;
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max = res->end - entry->offset;
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base = __pa(io_space[space_nr].mmio_base);
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base_port = IO_SPACE_BASE(space_nr);
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snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->common.name,
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base_port + min, base_port + max);
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/*
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* The SDM guarantees the legacy 0-64K space is sparse, but if the
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* mapping is done by the processor (not the bridge), ACPI may not
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* mark it as sparse.
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*/
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if (space_nr == 0)
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sparse = 1;
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resource = iospace->res;
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resource->name = name;
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resource->flags = IORESOURCE_MEM;
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resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
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resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
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if (insert_resource(&iomem_resource, resource)) {
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dev_err(dev,
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"can't allocate host bridge io space resource %pR\n",
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resource);
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goto free_resource;
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}
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entry->offset = base_port;
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res->start = min + base_port;
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res->end = max + base_port;
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resource_list_add_tail(iospace, &info->io_resources);
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return 0;
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free_resource:
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resource_list_free_entry(iospace);
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return -ENOSPC;
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}
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/*
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* An IO port or MMIO resource assigned to a PCI host bridge may be
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* consumed by the host bridge itself or available to its child
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* bus/devices. The ACPI specification defines a bit (Producer/Consumer)
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* to tell whether the resource is consumed by the host bridge itself,
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* but firmware hasn't used that bit consistently, so we can't rely on it.
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*
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* On x86 and IA64 platforms, all IO port and MMIO resources are assumed
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* to be available to child bus/devices except one special case:
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* IO port [0xCF8-0xCFF] is consumed by the host bridge itself
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* to access PCI configuration space.
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*
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* So explicitly filter out PCI CFG IO ports[0xCF8-0xCFF].
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*/
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static bool resource_is_pcicfg_ioport(struct resource *res)
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{
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return (res->flags & IORESOURCE_IO) &&
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res->start == 0xCF8 && res->end == 0xCFF;
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}
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static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
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{
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struct device *dev = &ci->bridge->dev;
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struct pci_root_info *info;
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struct resource *res;
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struct resource_entry *entry, *tmp;
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int status;
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status = acpi_pci_probe_root_resources(ci);
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if (status > 0) {
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info = container_of(ci, struct pci_root_info, common);
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resource_list_for_each_entry_safe(entry, tmp, &ci->resources) {
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res = entry->res;
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if (res->flags & IORESOURCE_MEM) {
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/*
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* HP's firmware has a hack to work around a
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* Windows bug. Ignore these tiny memory ranges.
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*/
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if (resource_size(res) <= 16) {
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resource_list_del(entry);
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insert_resource(&iomem_resource,
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entry->res);
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resource_list_add_tail(entry,
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&info->io_resources);
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}
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} else if (res->flags & IORESOURCE_IO) {
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if (resource_is_pcicfg_ioport(entry->res))
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resource_list_destroy_entry(entry);
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else if (add_io_space(dev, info, entry))
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resource_list_destroy_entry(entry);
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}
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}
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}
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return status;
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}
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static void pci_acpi_root_release_info(struct acpi_pci_root_info *ci)
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{
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struct pci_root_info *info;
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struct resource_entry *entry, *tmp;
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info = container_of(ci, struct pci_root_info, common);
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resource_list_for_each_entry_safe(entry, tmp, &info->io_resources) {
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release_resource(entry->res);
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resource_list_destroy_entry(entry);
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}
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kfree(info);
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}
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static struct acpi_pci_root_ops pci_acpi_root_ops = {
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.pci_ops = &pci_root_ops,
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.release_info = pci_acpi_root_release_info,
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.prepare_resources = pci_acpi_root_prepare_resources,
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};
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struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
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{
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struct acpi_device *device = root->device;
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struct pci_root_info *info;
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info = kzalloc(sizeof(*info), GFP_KERNEL);
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if (!info) {
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dev_err(&device->dev,
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"pci_bus %04x:%02x: ignored (out of memory)\n",
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root->segment, (int)root->secondary.start);
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return NULL;
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}
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info->controller.segment = root->segment;
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info->controller.companion = device;
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info->controller.node = acpi_get_node(device->handle);
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INIT_LIST_HEAD(&info->io_resources);
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return acpi_pci_root_create(root, &pci_acpi_root_ops,
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&info->common, &info->controller);
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}
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int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
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{
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/*
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* We pass NULL as parent to pci_create_root_bus(), so if it is not NULL
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* here, pci_create_root_bus() has been called by someone else and
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* sysdata is likely to be different from what we expect. Let it go in
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* that case.
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*/
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if (!bridge->dev.parent) {
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struct pci_controller *controller = bridge->bus->sysdata;
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ACPI_COMPANION_SET(&bridge->dev, controller->companion);
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}
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return 0;
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}
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void pcibios_fixup_device_resources(struct pci_dev *dev)
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{
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int idx;
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if (!dev->bus)
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return;
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for (idx = 0; idx < PCI_BRIDGE_RESOURCES; idx++) {
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struct resource *r = &dev->resource[idx];
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if (!r->flags || r->parent || !r->start)
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continue;
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pci_claim_resource(dev, idx);
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}
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}
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EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
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static void pcibios_fixup_bridge_resources(struct pci_dev *dev)
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{
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int idx;
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if (!dev->bus)
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return;
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for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
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struct resource *r = &dev->resource[idx];
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if (!r->flags || r->parent || !r->start)
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continue;
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pci_claim_bridge_resource(dev, idx);
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}
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}
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/*
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* Called after each bus is probed, but before its children are examined.
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*/
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void pcibios_fixup_bus(struct pci_bus *b)
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{
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struct pci_dev *dev;
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if (b->self) {
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pci_read_bridge_bases(b);
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pcibios_fixup_bridge_resources(b->self);
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}
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list_for_each_entry(dev, &b->devices, bus_list)
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pcibios_fixup_device_resources(dev);
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platform_pci_fixup_bus(b);
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}
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void pcibios_add_bus(struct pci_bus *bus)
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{
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acpi_pci_add_bus(bus);
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}
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void pcibios_remove_bus(struct pci_bus *bus)
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{
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acpi_pci_remove_bus(bus);
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}
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void pcibios_set_master (struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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int
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pcibios_enable_device (struct pci_dev *dev, int mask)
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{
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int ret;
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ret = pci_enable_resources(dev, mask);
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if (ret < 0)
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return ret;
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if (!dev->msi_enabled)
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return acpi_pci_irq_enable(dev);
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return 0;
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}
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void
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pcibios_disable_device (struct pci_dev *dev)
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{
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BUG_ON(atomic_read(&dev->enable_cnt));
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if (!dev->msi_enabled)
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acpi_pci_irq_disable(dev);
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}
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/**
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* ia64_pci_get_legacy_mem - generic legacy mem routine
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* @bus: bus to get legacy memory base address for
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*
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* Find the base of legacy memory for @bus. This is typically the first
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* megabyte of bus address space for @bus or is simply 0 on platforms whose
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* chipsets support legacy I/O and memory routing. Returns the base address
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* or an error pointer if an error occurred.
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*
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* This is the ia64 generic version of this routine. Other platforms
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* are free to override it with a machine vector.
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*/
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char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
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{
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return (char *)__IA64_UNCACHED_OFFSET;
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}
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/**
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* pci_mmap_legacy_page_range - map legacy memory space to userland
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* @bus: bus whose legacy space we're mapping
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* @vma: vma passed in by mmap
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*
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* Map legacy memory space for this device back to userspace using a machine
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* vector to get the base address.
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*/
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int
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pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state)
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{
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unsigned long size = vma->vm_end - vma->vm_start;
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pgprot_t prot;
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char *addr;
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/* We only support mmap'ing of legacy memory space */
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if (mmap_state != pci_mmap_mem)
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return -ENOSYS;
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/*
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* Avoid attribute aliasing. See Documentation/ia64/aliasing.txt
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* for more details.
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*/
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if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
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return -EINVAL;
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prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
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vma->vm_page_prot);
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addr = pci_get_legacy_mem(bus);
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if (IS_ERR(addr))
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return PTR_ERR(addr);
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vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
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vma->vm_page_prot = prot;
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if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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size, vma->vm_page_prot))
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return -EAGAIN;
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return 0;
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}
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/**
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* ia64_pci_legacy_read - read from legacy I/O space
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* @bus: bus to read
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* @port: legacy port value
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* @val: caller allocated storage for returned value
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* @size: number of bytes to read
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*
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* Simply reads @size bytes from @port and puts the result in @val.
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*
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* Again, this (and the write routine) are generic versions that can be
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* overridden by the platform. This is necessary on platforms that don't
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* support legacy I/O routing or that hard fail on legacy I/O timeouts.
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*/
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int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
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{
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int ret = size;
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switch (size) {
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case 1:
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*val = inb(port);
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break;
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case 2:
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*val = inw(port);
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break;
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case 4:
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*val = inl(port);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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/**
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* ia64_pci_legacy_write - perform a legacy I/O write
|
|
* @bus: bus pointer
|
|
* @port: port to write
|
|
* @val: value to write
|
|
* @size: number of bytes to write from @val
|
|
*
|
|
* Simply writes @size bytes of @val to @port.
|
|
*/
|
|
int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
|
|
{
|
|
int ret = size;
|
|
|
|
switch (size) {
|
|
case 1:
|
|
outb(val, port);
|
|
break;
|
|
case 2:
|
|
outw(val, port);
|
|
break;
|
|
case 4:
|
|
outl(val, port);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* set_pci_cacheline_size - determine cacheline size for PCI devices
|
|
*
|
|
* We want to use the line-size of the outer-most cache. We assume
|
|
* that this line-size is the same for all CPUs.
|
|
*
|
|
* Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
|
|
*/
|
|
static void __init set_pci_dfl_cacheline_size(void)
|
|
{
|
|
unsigned long levels, unique_caches;
|
|
long status;
|
|
pal_cache_config_info_t cci;
|
|
|
|
status = ia64_pal_cache_summary(&levels, &unique_caches);
|
|
if (status != 0) {
|
|
pr_err("%s: ia64_pal_cache_summary() failed "
|
|
"(status=%ld)\n", __func__, status);
|
|
return;
|
|
}
|
|
|
|
status = ia64_pal_cache_config_info(levels - 1,
|
|
/* cache_type (data_or_unified)= */ 2, &cci);
|
|
if (status != 0) {
|
|
pr_err("%s: ia64_pal_cache_config_info() failed "
|
|
"(status=%ld)\n", __func__, status);
|
|
return;
|
|
}
|
|
pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
|
|
}
|
|
|
|
u64 ia64_dma_get_required_mask(struct device *dev)
|
|
{
|
|
u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT);
|
|
u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT));
|
|
u64 mask;
|
|
|
|
if (!high_totalram) {
|
|
/* convert to mask just covering totalram */
|
|
low_totalram = (1 << (fls(low_totalram) - 1));
|
|
low_totalram += low_totalram - 1;
|
|
mask = low_totalram;
|
|
} else {
|
|
high_totalram = (1 << (fls(high_totalram) - 1));
|
|
high_totalram += high_totalram - 1;
|
|
mask = (((u64)high_totalram) << 32) + 0xffffffff;
|
|
}
|
|
return mask;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask);
|
|
|
|
u64 dma_get_required_mask(struct device *dev)
|
|
{
|
|
return platform_dma_get_required_mask(dev);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dma_get_required_mask);
|
|
|
|
static int __init pcibios_init(void)
|
|
{
|
|
set_pci_dfl_cacheline_size();
|
|
return 0;
|
|
}
|
|
|
|
subsys_initcall(pcibios_init);
|