![Greg Kroah-Hartman](/assets/img/avatar_default.png)
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
516 lines
17 KiB
C
516 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/sparc/math-emu/math.c
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*
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* Copyright (C) 1998 Peter Maydell (pmaydell@chiark.greenend.org.uk)
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* Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
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* Copyright (C) 1999 David S. Miller (davem@redhat.com)
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*
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* This is a good place to start if you're trying to understand the
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* emulation code, because it's pretty simple. What we do is
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* essentially analyse the instruction to work out what the operation
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* is and which registers are involved. We then execute the appropriate
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* FXXXX function. [The floating point queue introduces a minor wrinkle;
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* see below...]
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* The fxxxxx.c files each emulate a single insn. They look relatively
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* simple because the complexity is hidden away in an unholy tangle
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* of preprocessor macros.
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*
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* The first layer of macros is single.h, double.h, quad.h. Generally
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* these files define macros for working with floating point numbers
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* of the three IEEE formats. FP_ADD_D(R,A,B) is for adding doubles,
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* for instance. These macros are usually defined as calls to more
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* generic macros (in this case _FP_ADD(D,2,R,X,Y) where the number
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* of machine words required to store the given IEEE format is passed
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* as a parameter. [double.h and co check the number of bits in a word
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* and define FP_ADD_D & co appropriately].
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* The generic macros are defined in op-common.h. This is where all
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* the grotty stuff like handling NaNs is coded. To handle the possible
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* word sizes macros in op-common.h use macros like _FP_FRAC_SLL_##wc()
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* where wc is the 'number of machine words' parameter (here 2).
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* These are defined in the third layer of macros: op-1.h, op-2.h
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* and op-4.h. These handle operations on floating point numbers composed
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* of 1,2 and 4 machine words respectively. [For example, on sparc64
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* doubles are one machine word so macros in double.h eventually use
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* constructs in op-1.h, but on sparc32 they use op-2.h definitions.]
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* soft-fp.h is on the same level as op-common.h, and defines some
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* macros which are independent of both word size and FP format.
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* Finally, sfp-machine.h is the machine dependent part of the
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* code: it defines the word size and what type a word is. It also
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* defines how _FP_MUL_MEAT_t() maps to _FP_MUL_MEAT_n_* : op-n.h
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* provide several possible flavours of multiply algorithm, most
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* of which require that you supply some form of asm or C primitive to
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* do the actual multiply. (such asm primitives should be defined
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* in sfp-machine.h too). udivmodti4.c is the same sort of thing.
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*
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* There may be some errors here because I'm working from a
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* SPARC architecture manual V9, and what I really want is V8...
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* Also, the insns which can generate exceptions seem to be a
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* greater subset of the FPops than for V9 (for example, FCMPED
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* has to be emulated on V8). So I think I'm going to have
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* to emulate them all just to be on the safe side...
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*
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* Emulation routines originate from soft-fp package, which is
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* part of glibc and has appropriate copyrights in it (allegedly).
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*
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* NB: on sparc int == long == 4 bytes, long long == 8 bytes.
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* Most bits of the kernel seem to go for long rather than int,
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* so we follow that practice...
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*/
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/* TODO:
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* fpsave() saves the FP queue but fpload() doesn't reload it.
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* Therefore when we context switch or change FPU ownership
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* we have to check to see if the queue had anything in it and
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* emulate it if it did. This is going to be a pain.
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*/
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/perf_event.h>
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#include <linux/uaccess.h>
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#include "sfp-util_32.h"
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#include <math-emu/soft-fp.h>
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#include <math-emu/single.h>
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#include <math-emu/double.h>
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#include <math-emu/quad.h>
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#define FLOATFUNC(x) extern int x(void *,void *,void *)
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/* The Vn labels indicate what version of the SPARC architecture gas thinks
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* each insn is. This is from the binutils source :->
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*/
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/* quadword instructions */
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#define FSQRTQ 0x02b /* v8 */
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#define FADDQ 0x043 /* v8 */
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#define FSUBQ 0x047 /* v8 */
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#define FMULQ 0x04b /* v8 */
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#define FDIVQ 0x04f /* v8 */
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#define FDMULQ 0x06e /* v8 */
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#define FQTOS 0x0c7 /* v8 */
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#define FQTOD 0x0cb /* v8 */
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#define FITOQ 0x0cc /* v8 */
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#define FSTOQ 0x0cd /* v8 */
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#define FDTOQ 0x0ce /* v8 */
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#define FQTOI 0x0d3 /* v8 */
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#define FCMPQ 0x053 /* v8 */
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#define FCMPEQ 0x057 /* v8 */
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/* single/double instructions (subnormal): should all work */
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#define FSQRTS 0x029 /* v7 */
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#define FSQRTD 0x02a /* v7 */
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#define FADDS 0x041 /* v6 */
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#define FADDD 0x042 /* v6 */
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#define FSUBS 0x045 /* v6 */
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#define FSUBD 0x046 /* v6 */
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#define FMULS 0x049 /* v6 */
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#define FMULD 0x04a /* v6 */
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#define FDIVS 0x04d /* v6 */
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#define FDIVD 0x04e /* v6 */
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#define FSMULD 0x069 /* v6 */
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#define FDTOS 0x0c6 /* v6 */
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#define FSTOD 0x0c9 /* v6 */
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#define FSTOI 0x0d1 /* v6 */
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#define FDTOI 0x0d2 /* v6 */
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#define FABSS 0x009 /* v6 */
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#define FCMPS 0x051 /* v6 */
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#define FCMPES 0x055 /* v6 */
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#define FCMPD 0x052 /* v6 */
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#define FCMPED 0x056 /* v6 */
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#define FMOVS 0x001 /* v6 */
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#define FNEGS 0x005 /* v6 */
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#define FITOS 0x0c4 /* v6 */
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#define FITOD 0x0c8 /* v6 */
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#define FSR_TEM_SHIFT 23UL
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#define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
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#define FSR_AEXC_SHIFT 5UL
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#define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
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#define FSR_CEXC_SHIFT 0UL
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#define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
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static int do_one_mathemu(u32 insn, unsigned long *fsr, unsigned long *fregs);
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/* Unlike the Sparc64 version (which has a struct fpustate), we
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* pass the taskstruct corresponding to the task which currently owns the
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* FPU. This is partly because we don't have the fpustate struct and
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* partly because the task owning the FPU isn't always current (as is
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* the case for the Sparc64 port). This is probably SMP-related...
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* This function returns 1 if all queued insns were emulated successfully.
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* The test for unimplemented FPop in kernel mode has been moved into
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* kernel/traps.c for simplicity.
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*/
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int do_mathemu(struct pt_regs *regs, struct task_struct *fpt)
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{
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/* regs->pc isn't necessarily the PC at which the offending insn is sitting.
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* The FPU maintains a queue of FPops which cause traps.
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* When it hits an instruction that requires that the trapped op succeeded
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* (usually because it reads a reg. that the trapped op wrote) then it
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* causes this exception. We need to emulate all the insns on the queue
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* and then allow the op to proceed.
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* This code should also handle the case where the trap was precise,
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* in which case the queue length is zero and regs->pc points at the
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* single FPop to be emulated. (this case is untested, though :->)
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* You'll need this case if you want to be able to emulate all FPops
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* because the FPU either doesn't exist or has been software-disabled.
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* [The UltraSPARC makes FP a precise trap; this isn't as stupid as it
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* might sound because the Ultra does funky things with a superscalar
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* architecture.]
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*/
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/* You wouldn't believe how often I typed 'ftp' when I meant 'fpt' :-> */
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int i;
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int retcode = 0; /* assume all succeed */
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unsigned long insn;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
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#ifdef DEBUG_MATHEMU
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printk("In do_mathemu()... pc is %08lx\n", regs->pc);
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printk("fpqdepth is %ld\n", fpt->thread.fpqdepth);
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for (i = 0; i < fpt->thread.fpqdepth; i++)
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printk("%d: %08lx at %08lx\n", i, fpt->thread.fpqueue[i].insn,
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(unsigned long)fpt->thread.fpqueue[i].insn_addr);
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#endif
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if (fpt->thread.fpqdepth == 0) { /* no queue, guilty insn is at regs->pc */
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#ifdef DEBUG_MATHEMU
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printk("precise trap at %08lx\n", regs->pc);
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#endif
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if (!get_user(insn, (u32 __user *) regs->pc)) {
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retcode = do_one_mathemu(insn, &fpt->thread.fsr, fpt->thread.float_regs);
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if (retcode) {
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/* in this case we need to fix up PC & nPC */
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regs->pc = regs->npc;
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regs->npc += 4;
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}
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}
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return retcode;
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}
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/* Normal case: need to empty the queue... */
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for (i = 0; i < fpt->thread.fpqdepth; i++) {
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retcode = do_one_mathemu(fpt->thread.fpqueue[i].insn, &(fpt->thread.fsr), fpt->thread.float_regs);
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if (!retcode) /* insn failed, no point doing any more */
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break;
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}
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/* Now empty the queue and clear the queue_not_empty flag */
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if (retcode)
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fpt->thread.fsr &= ~(0x3000 | FSR_CEXC_MASK);
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else
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fpt->thread.fsr &= ~0x3000;
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fpt->thread.fpqdepth = 0;
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return retcode;
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}
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/* All routines returning an exception to raise should detect
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* such exceptions _before_ rounding to be consistent with
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* the behavior of the hardware in the implemented cases
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* (and thus with the recommendations in the V9 architecture
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* manual).
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*
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* We return 0 if a SIGFPE should be sent, 1 otherwise.
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*/
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static inline int record_exception(unsigned long *pfsr, int eflag)
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{
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unsigned long fsr = *pfsr;
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int would_trap;
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/* Determine if this exception would have generated a trap. */
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would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
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/* If trapping, we only want to signal one bit. */
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if (would_trap != 0) {
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eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
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if ((eflag & (eflag - 1)) != 0) {
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if (eflag & FP_EX_INVALID)
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eflag = FP_EX_INVALID;
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else if (eflag & FP_EX_OVERFLOW)
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eflag = FP_EX_OVERFLOW;
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else if (eflag & FP_EX_UNDERFLOW)
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eflag = FP_EX_UNDERFLOW;
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else if (eflag & FP_EX_DIVZERO)
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eflag = FP_EX_DIVZERO;
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else if (eflag & FP_EX_INEXACT)
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eflag = FP_EX_INEXACT;
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}
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}
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/* Set CEXC, here is the rule:
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*
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* In general all FPU ops will set one and only one
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* bit in the CEXC field, this is always the case
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* when the IEEE exception trap is enabled in TEM.
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*/
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fsr &= ~(FSR_CEXC_MASK);
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fsr |= ((long)eflag << FSR_CEXC_SHIFT);
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/* Set the AEXC field, rule is:
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*
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* If a trap would not be generated, the
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* CEXC just generated is OR'd into the
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* existing value of AEXC.
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*/
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if (would_trap == 0)
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fsr |= ((long)eflag << FSR_AEXC_SHIFT);
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/* If trapping, indicate fault trap type IEEE. */
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if (would_trap != 0)
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fsr |= (1UL << 14);
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*pfsr = fsr;
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return (would_trap ? 0 : 1);
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}
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typedef union {
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u32 s;
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u64 d;
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u64 q[2];
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} *argp;
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static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs)
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{
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/* Emulate the given insn, updating fsr and fregs appropriately. */
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int type = 0;
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/* r is rd, b is rs2 and a is rs1. The *u arg tells
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whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
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non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
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#define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6)
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int freg;
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argp rs1 = NULL, rs2 = NULL, rd = NULL;
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FP_DECL_EX;
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FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
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FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
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FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
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int IR;
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long fsr;
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#ifdef DEBUG_MATHEMU
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printk("In do_mathemu(), emulating %08lx\n", insn);
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#endif
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if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
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switch ((insn >> 5) & 0x1ff) {
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case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
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case FADDQ:
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case FSUBQ:
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case FMULQ:
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case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
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case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
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case FQTOS: TYPE(3,1,1,3,1,0,0); break;
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case FQTOD: TYPE(3,2,1,3,1,0,0); break;
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case FITOQ: TYPE(3,3,1,1,0,0,0); break;
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case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
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case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
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case FQTOI: TYPE(3,1,0,3,1,0,0); break;
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case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
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case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
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case FADDD:
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case FSUBD:
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case FMULD:
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case FDIVD: TYPE(2,2,1,2,1,2,1); break;
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case FADDS:
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case FSUBS:
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case FMULS:
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case FDIVS: TYPE(2,1,1,1,1,1,1); break;
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case FSMULD: TYPE(2,2,1,1,1,1,1); break;
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case FDTOS: TYPE(2,1,1,2,1,0,0); break;
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case FSTOD: TYPE(2,2,1,1,1,0,0); break;
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case FSTOI: TYPE(2,1,0,1,1,0,0); break;
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case FDTOI: TYPE(2,1,0,2,1,0,0); break;
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case FITOS: TYPE(2,1,1,1,0,0,0); break;
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case FITOD: TYPE(2,2,1,1,0,0,0); break;
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case FMOVS:
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case FABSS:
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case FNEGS: TYPE(2,1,0,1,0,0,0); break;
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}
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} else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
|
|
switch ((insn >> 5) & 0x1ff) {
|
|
case FCMPS: TYPE(3,0,0,1,1,1,1); break;
|
|
case FCMPES: TYPE(3,0,0,1,1,1,1); break;
|
|
case FCMPD: TYPE(3,0,0,2,1,2,1); break;
|
|
case FCMPED: TYPE(3,0,0,2,1,2,1); break;
|
|
case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
|
|
case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
|
|
}
|
|
}
|
|
|
|
if (!type) { /* oops, didn't recognise that FPop */
|
|
#ifdef DEBUG_MATHEMU
|
|
printk("attempt to emulate unrecognised FPop!\n");
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
/* Decode the registers to be used */
|
|
freg = (*pfsr >> 14) & 0xf;
|
|
|
|
*pfsr &= ~0x1c000; /* clear the traptype bits */
|
|
|
|
freg = ((insn >> 14) & 0x1f);
|
|
switch (type & 0x3) { /* is rs1 single, double or quad? */
|
|
case 3:
|
|
if (freg & 3) { /* quadwords must have bits 4&5 of the */
|
|
/* encoded reg. number set to zero. */
|
|
*pfsr |= (6 << 14);
|
|
return 0; /* simulate invalid_fp_register exception */
|
|
}
|
|
/* fall through */
|
|
case 2:
|
|
if (freg & 1) { /* doublewords must have bit 5 zeroed */
|
|
*pfsr |= (6 << 14);
|
|
return 0;
|
|
}
|
|
}
|
|
rs1 = (argp)&fregs[freg];
|
|
switch (type & 0x7) {
|
|
case 7: FP_UNPACK_QP (QA, rs1); break;
|
|
case 6: FP_UNPACK_DP (DA, rs1); break;
|
|
case 5: FP_UNPACK_SP (SA, rs1); break;
|
|
}
|
|
freg = (insn & 0x1f);
|
|
switch ((type >> 3) & 0x3) { /* same again for rs2 */
|
|
case 3:
|
|
if (freg & 3) { /* quadwords must have bits 4&5 of the */
|
|
/* encoded reg. number set to zero. */
|
|
*pfsr |= (6 << 14);
|
|
return 0; /* simulate invalid_fp_register exception */
|
|
}
|
|
/* fall through */
|
|
case 2:
|
|
if (freg & 1) { /* doublewords must have bit 5 zeroed */
|
|
*pfsr |= (6 << 14);
|
|
return 0;
|
|
}
|
|
}
|
|
rs2 = (argp)&fregs[freg];
|
|
switch ((type >> 3) & 0x7) {
|
|
case 7: FP_UNPACK_QP (QB, rs2); break;
|
|
case 6: FP_UNPACK_DP (DB, rs2); break;
|
|
case 5: FP_UNPACK_SP (SB, rs2); break;
|
|
}
|
|
freg = ((insn >> 25) & 0x1f);
|
|
switch ((type >> 6) & 0x3) { /* and finally rd. This one's a bit different */
|
|
case 0: /* dest is fcc. (this must be FCMPQ or FCMPEQ) */
|
|
if (freg) { /* V8 has only one set of condition codes, so */
|
|
/* anything but 0 in the rd field is an error */
|
|
*pfsr |= (6 << 14); /* (should probably flag as invalid opcode */
|
|
return 0; /* but SIGFPE will do :-> ) */
|
|
}
|
|
break;
|
|
case 3:
|
|
if (freg & 3) { /* quadwords must have bits 4&5 of the */
|
|
/* encoded reg. number set to zero. */
|
|
*pfsr |= (6 << 14);
|
|
return 0; /* simulate invalid_fp_register exception */
|
|
}
|
|
/* fall through */
|
|
case 2:
|
|
if (freg & 1) { /* doublewords must have bit 5 zeroed */
|
|
*pfsr |= (6 << 14);
|
|
return 0;
|
|
}
|
|
/* fall through */
|
|
case 1:
|
|
rd = (void *)&fregs[freg];
|
|
break;
|
|
}
|
|
#ifdef DEBUG_MATHEMU
|
|
printk("executing insn...\n");
|
|
#endif
|
|
/* do the Right Thing */
|
|
switch ((insn >> 5) & 0x1ff) {
|
|
/* + */
|
|
case FADDS: FP_ADD_S (SR, SA, SB); break;
|
|
case FADDD: FP_ADD_D (DR, DA, DB); break;
|
|
case FADDQ: FP_ADD_Q (QR, QA, QB); break;
|
|
/* - */
|
|
case FSUBS: FP_SUB_S (SR, SA, SB); break;
|
|
case FSUBD: FP_SUB_D (DR, DA, DB); break;
|
|
case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
|
|
/* * */
|
|
case FMULS: FP_MUL_S (SR, SA, SB); break;
|
|
case FSMULD: FP_CONV (D, S, 2, 1, DA, SA);
|
|
FP_CONV (D, S, 2, 1, DB, SB);
|
|
case FMULD: FP_MUL_D (DR, DA, DB); break;
|
|
case FDMULQ: FP_CONV (Q, D, 4, 2, QA, DA);
|
|
FP_CONV (Q, D, 4, 2, QB, DB);
|
|
case FMULQ: FP_MUL_Q (QR, QA, QB); break;
|
|
/* / */
|
|
case FDIVS: FP_DIV_S (SR, SA, SB); break;
|
|
case FDIVD: FP_DIV_D (DR, DA, DB); break;
|
|
case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
|
|
/* sqrt */
|
|
case FSQRTS: FP_SQRT_S (SR, SB); break;
|
|
case FSQRTD: FP_SQRT_D (DR, DB); break;
|
|
case FSQRTQ: FP_SQRT_Q (QR, QB); break;
|
|
/* mov */
|
|
case FMOVS: rd->s = rs2->s; break;
|
|
case FABSS: rd->s = rs2->s & 0x7fffffff; break;
|
|
case FNEGS: rd->s = rs2->s ^ 0x80000000; break;
|
|
/* float to int */
|
|
case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
|
|
case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
|
|
case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
|
|
/* int to float */
|
|
case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
|
|
case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
|
|
case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
|
|
/* float to float */
|
|
case FSTOD: FP_CONV (D, S, 2, 1, DR, SB); break;
|
|
case FSTOQ: FP_CONV (Q, S, 4, 1, QR, SB); break;
|
|
case FDTOQ: FP_CONV (Q, D, 4, 2, QR, DB); break;
|
|
case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break;
|
|
case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break;
|
|
case FQTOD: FP_CONV (D, Q, 2, 4, DR, QB); break;
|
|
/* comparison */
|
|
case FCMPS:
|
|
case FCMPES:
|
|
FP_CMP_S(IR, SB, SA, 3);
|
|
if (IR == 3 &&
|
|
(((insn >> 5) & 0x1ff) == FCMPES ||
|
|
FP_ISSIGNAN_S(SA) ||
|
|
FP_ISSIGNAN_S(SB)))
|
|
FP_SET_EXCEPTION (FP_EX_INVALID);
|
|
break;
|
|
case FCMPD:
|
|
case FCMPED:
|
|
FP_CMP_D(IR, DB, DA, 3);
|
|
if (IR == 3 &&
|
|
(((insn >> 5) & 0x1ff) == FCMPED ||
|
|
FP_ISSIGNAN_D(DA) ||
|
|
FP_ISSIGNAN_D(DB)))
|
|
FP_SET_EXCEPTION (FP_EX_INVALID);
|
|
break;
|
|
case FCMPQ:
|
|
case FCMPEQ:
|
|
FP_CMP_Q(IR, QB, QA, 3);
|
|
if (IR == 3 &&
|
|
(((insn >> 5) & 0x1ff) == FCMPEQ ||
|
|
FP_ISSIGNAN_Q(QA) ||
|
|
FP_ISSIGNAN_Q(QB)))
|
|
FP_SET_EXCEPTION (FP_EX_INVALID);
|
|
}
|
|
if (!FP_INHIBIT_RESULTS) {
|
|
switch ((type >> 6) & 0x7) {
|
|
case 0: fsr = *pfsr;
|
|
if (IR == -1) IR = 2;
|
|
/* fcc is always fcc0 */
|
|
fsr &= ~0xc00; fsr |= (IR << 10);
|
|
*pfsr = fsr;
|
|
break;
|
|
case 1: rd->s = IR; break;
|
|
case 5: FP_PACK_SP (rd, SR); break;
|
|
case 6: FP_PACK_DP (rd, DR); break;
|
|
case 7: FP_PACK_QP (rd, QR); break;
|
|
}
|
|
}
|
|
if (_fex == 0)
|
|
return 1; /* success! */
|
|
return record_exception(pfsr, _fex);
|
|
}
|