b7f8292c96
Some saa7115-based cards use a different crystal frequency and a different audio clock generation. Add a new VIDIOC_INT_S_CRYSTAL_FREQ command to be able to set these values. Also change the default APLL setting to 0. It makes no sense to have the audio clock independent from the video clock, this can lead to audio/video synchronization problems. Setting this to 0 is also consistent with the old saa7114.c source and the way the Hauppauge Windows driver sets it. Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
47 lines
1.7 KiB
C
47 lines
1.7 KiB
C
/*
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saa7115.h - definition for saa7113/4/5 inputs and frequency flags
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Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _SAA7115_H_
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#define _SAA7115_H_
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/* SAA7113/4/5 HW inputs */
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#define SAA7115_COMPOSITE0 0
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#define SAA7115_COMPOSITE1 1
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#define SAA7115_COMPOSITE2 2
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#define SAA7115_COMPOSITE3 3
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#define SAA7115_COMPOSITE4 4 /* not available for the saa7113 */
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#define SAA7115_COMPOSITE5 5 /* not available for the saa7113 */
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#define SAA7115_SVIDEO0 6
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#define SAA7115_SVIDEO1 7
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#define SAA7115_SVIDEO2 8
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#define SAA7115_SVIDEO3 9
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/* SAA7115 v4l2_crystal_freq frequency values */
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#define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */
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#define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */
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/* SAA7115 v4l2_crystal_freq audio clock control flags */
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#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */
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#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
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#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
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#endif
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