717b8fae38
Current code defines some bits with left shift to the proper bit defined in datasheet, but some don't. Unify the definition with proper left shift and adjust the code accordingly. Signed-off-by: Axel Lin <axel.lin@gmail.com> Acked-by: Brian Austin <brian.austin@cirrus.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
228 lines
9.1 KiB
C
228 lines
9.1 KiB
C
/*
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* ALSA SoC CS42L73 codec driver
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*
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* Copyright 2011 Cirrus Logic, Inc.
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*
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* Author: Georgi Vlaev <joe@nucleusys.com>
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* Brian Austin <brian.austin@cirrus.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __CS42L73_H__
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#define __CS42L73_H__
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/* I2C Registers */
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/* I2C Address: 1001010[R/W] - 10010100 = 0x94(Write); 10010101 = 0x95(Read) */
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#define CS42L73_CHIP_ID 0x4a
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#define CS42L73_DEVID_AB 0x01 /* Device ID A & B [RO]. */
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#define CS42L73_DEVID_CD 0x02 /* Device ID C & D [RO]. */
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#define CS42L73_DEVID_E 0x03 /* Device ID E [RO]. */
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#define CS42L73_REVID 0x05 /* Revision ID [RO]. */
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#define CS42L73_PWRCTL1 0x06 /* Power Control 1. */
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#define CS42L73_PWRCTL2 0x07 /* Power Control 2. */
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#define CS42L73_PWRCTL3 0x08 /* Power Control 3. */
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#define CS42L73_CPFCHC 0x09 /* Charge Pump Freq. Class H Ctl. */
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#define CS42L73_OLMBMSDC 0x0A /* Output Load, MIC Bias, MIC2 SDT */
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#define CS42L73_DMMCC 0x0B /* Digital MIC & Master Clock Ctl. */
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#define CS42L73_XSPC 0x0C /* Auxiliary Serial Port (XSP) Ctl. */
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#define CS42L73_XSPMMCC 0x0D /* XSP Master Mode Clocking Control. */
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#define CS42L73_ASPC 0x0E /* Audio Serial Port (ASP) Control. */
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#define CS42L73_ASPMMCC 0x0F /* ASP Master Mode Clocking Control. */
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#define CS42L73_VSPC 0x10 /* Voice Serial Port (VSP) Control. */
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#define CS42L73_VSPMMCC 0x11 /* VSP Master Mode Clocking Control. */
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#define CS42L73_VXSPFS 0x12 /* VSP & XSP Sample Rate. */
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#define CS42L73_MIOPC 0x13 /* Misc. Input & Output Path Control. */
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#define CS42L73_ADCIPC 0x14 /* ADC/IP Control. */
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#define CS42L73_MICAPREPGAAVOL 0x15 /* MIC 1 [A] PreAmp, PGAA Vol. */
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#define CS42L73_MICBPREPGABVOL 0x16 /* MIC 2 [B] PreAmp, PGAB Vol. */
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#define CS42L73_IPADVOL 0x17 /* Input Pat7h A Digital Volume. */
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#define CS42L73_IPBDVOL 0x18 /* Input Path B Digital Volume. */
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#define CS42L73_PBDC 0x19 /* Playback Digital Control. */
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#define CS42L73_HLADVOL 0x1A /* HP/Line A Out Digital Vol. */
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#define CS42L73_HLBDVOL 0x1B /* HP/Line B Out Digital Vol. */
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#define CS42L73_SPKDVOL 0x1C /* Spkphone Out [A] Digital Vol. */
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#define CS42L73_ESLDVOL 0x1D /* Ear/Spkphone LO [B] Digital */
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#define CS42L73_HPAAVOL 0x1E /* HP A Analog Volume. */
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#define CS42L73_HPBAVOL 0x1F /* HP B Analog Volume. */
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#define CS42L73_LOAAVOL 0x20 /* Line Out A Analog Volume. */
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#define CS42L73_LOBAVOL 0x21 /* Line Out B Analog Volume. */
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#define CS42L73_STRINV 0x22 /* Stereo Input Path Adv. Vol. */
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#define CS42L73_XSPINV 0x23 /* Auxiliary Port Input Advisory Vol. */
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#define CS42L73_ASPINV 0x24 /* Audio Port Input Advisory Vol. */
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#define CS42L73_VSPINV 0x25 /* Voice Port Input Advisory Vol. */
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#define CS42L73_LIMARATEHL 0x26 /* Lmtr Attack Rate HP/Line. */
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#define CS42L73_LIMRRATEHL 0x27 /* Lmtr Ctl, Rel.Rate HP/Line. */
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#define CS42L73_LMAXHL 0x28 /* Lmtr Thresholds HP/Line. */
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#define CS42L73_LIMARATESPK 0x29 /* Lmtr Attack Rate Spkphone [A]. */
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#define CS42L73_LIMRRATESPK 0x2A /* Lmtr Ctl,Release Rate Spk. [A]. */
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#define CS42L73_LMAXSPK 0x2B /* Lmtr Thresholds Spkphone [A]. */
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#define CS42L73_LIMARATEESL 0x2C /* Lmtr Attack Rate */
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#define CS42L73_LIMRRATEESL 0x2D /* Lmtr Ctl,Release Rate */
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#define CS42L73_LMAXESL 0x2E /* Lmtr Thresholds */
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#define CS42L73_ALCARATE 0x2F /* ALC Enable, Attack Rate AB. */
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#define CS42L73_ALCRRATE 0x30 /* ALC Release Rate AB. */
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#define CS42L73_ALCMINMAX 0x31 /* ALC Thresholds AB. */
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#define CS42L73_NGCAB 0x32 /* Noise Gate Ctl AB. */
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#define CS42L73_ALCNGMC 0x33 /* ALC & Noise Gate Misc Ctl. */
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#define CS42L73_MIXERCTL 0x34 /* Mixer Control. */
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#define CS42L73_HLAIPAA 0x35 /* HP/LO Left Mixer: L. */
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#define CS42L73_HLBIPBA 0x36 /* HP/LO Right Mixer: R. */
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#define CS42L73_HLAXSPAA 0x37 /* HP/LO Left Mixer: XSP L */
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#define CS42L73_HLBXSPBA 0x38 /* HP/LO Right Mixer: XSP R */
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#define CS42L73_HLAASPAA 0x39 /* HP/LO Left Mixer: ASP L */
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#define CS42L73_HLBASPBA 0x3A /* HP/LO Right Mixer: ASP R */
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#define CS42L73_HLAVSPMA 0x3B /* HP/LO Left Mixer: VSP. */
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#define CS42L73_HLBVSPMA 0x3C /* HP/LO Right Mixer: VSP */
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#define CS42L73_XSPAIPAA 0x3D /* XSP Left Mixer: Left */
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#define CS42L73_XSPBIPBA 0x3E /* XSP Rt. Mixer: Right */
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#define CS42L73_XSPAXSPAA 0x3F /* XSP Left Mixer: XSP L */
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#define CS42L73_XSPBXSPBA 0x40 /* XSP Rt. Mixer: XSP R */
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#define CS42L73_XSPAASPAA 0x41 /* XSP Left Mixer: ASP L */
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#define CS42L73_XSPAASPBA 0x42 /* XSP Rt. Mixer: ASP R */
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#define CS42L73_XSPAVSPMA 0x43 /* XSP Left Mixer: VSP */
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#define CS42L73_XSPBVSPMA 0x44 /* XSP Rt. Mixer: VSP */
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#define CS42L73_ASPAIPAA 0x45 /* ASP Left Mixer: Left */
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#define CS42L73_ASPBIPBA 0x46 /* ASP Rt. Mixer: Right */
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#define CS42L73_ASPAXSPAA 0x47 /* ASP Left Mixer: XSP L */
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#define CS42L73_ASPBXSPBA 0x48 /* ASP Rt. Mixer: XSP R */
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#define CS42L73_ASPAASPAA 0x49 /* ASP Left Mixer: ASP L */
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#define CS42L73_ASPBASPBA 0x4A /* ASP Rt. Mixer: ASP R */
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#define CS42L73_ASPAVSPMA 0x4B /* ASP Left Mixer: VSP */
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#define CS42L73_ASPBVSPMA 0x4C /* ASP Rt. Mixer: VSP */
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#define CS42L73_VSPAIPAA 0x4D /* VSP Left Mixer: Left */
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#define CS42L73_VSPBIPBA 0x4E /* VSP Rt. Mixer: Right */
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#define CS42L73_VSPAXSPAA 0x4F /* VSP Left Mixer: XSP L */
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#define CS42L73_VSPBXSPBA 0x50 /* VSP Rt. Mixer: XSP R */
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#define CS42L73_VSPAASPAA 0x51 /* VSP Left Mixer: ASP Left */
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#define CS42L73_VSPBASPBA 0x52 /* VSP Rt. Mixer: ASP Right */
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#define CS42L73_VSPAVSPMA 0x53 /* VSP Left Mixer: VSP */
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#define CS42L73_VSPBVSPMA 0x54 /* VSP Rt. Mixer: VSP */
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#define CS42L73_MMIXCTL 0x55 /* Mono Mixer Controls. */
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#define CS42L73_SPKMIPMA 0x56 /* SPK Mono Mixer: In. Path */
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#define CS42L73_SPKMXSPA 0x57 /* SPK Mono Mixer: XSP Mono/L/R Att. */
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#define CS42L73_SPKMASPA 0x58 /* SPK Mono Mixer: ASP Mono/L/R Att. */
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#define CS42L73_SPKMVSPMA 0x59 /* SPK Mono Mixer: VSP Mono Atten. */
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#define CS42L73_ESLMIPMA 0x5A /* Ear/SpLO Mono Mixer: */
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#define CS42L73_ESLMXSPA 0x5B /* Ear/SpLO Mono Mixer: XSP */
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#define CS42L73_ESLMASPA 0x5C /* Ear/SpLO Mono Mixer: ASP */
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#define CS42L73_ESLMVSPMA 0x5D /* Ear/SpLO Mono Mixer: VSP */
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#define CS42L73_IM1 0x5E /* Interrupt Mask 1. */
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#define CS42L73_IM2 0x5F /* Interrupt Mask 2. */
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#define CS42L73_IS1 0x60 /* Interrupt Status 1 [RO]. */
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#define CS42L73_IS2 0x61 /* Interrupt Status 2 [RO]. */
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#define CS42L73_MAX_REGISTER 0x61 /* Total Registers */
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/* Bitfield Definitions */
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/* CS42L73_PWRCTL1 */
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#define PDN_ADCB (1 << 7)
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#define PDN_DMICB (1 << 6)
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#define PDN_ADCA (1 << 5)
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#define PDN_DMICA (1 << 4)
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#define PDN_LDO (1 << 2)
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#define DISCHG_FILT (1 << 1)
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#define PDN (1 << 0)
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/* CS42L73_PWRCTL2 */
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#define PDN_MIC2_BIAS (1 << 7)
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#define PDN_MIC1_BIAS (1 << 6)
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#define PDN_VSP (1 << 4)
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#define PDN_ASP_SDOUT (1 << 3)
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#define PDN_ASP_SDIN (1 << 2)
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#define PDN_XSP_SDOUT (1 << 1)
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#define PDN_XSP_SDIN (1 << 0)
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/* CS42L73_PWRCTL3 */
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#define PDN_THMS (1 << 5)
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#define PDN_SPKLO (1 << 4)
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#define PDN_EAR (1 << 3)
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#define PDN_SPK (1 << 2)
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#define PDN_LO (1 << 1)
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#define PDN_HP (1 << 0)
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/* Thermal Overload Detect. Requires interrupt ... */
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#define THMOVLD_150C 0
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#define THMOVLD_132C 1
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#define THMOVLD_115C 2
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#define THMOVLD_098C 3
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/* CS42L73_ASPC, CS42L73_XSPC, CS42L73_VSPC */
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#define SP_3ST (1 << 7)
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#define SPDIF_I2S (0 << 6)
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#define SPDIF_PCM (1 << 6)
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#define PCM_MODE0 (0 << 4)
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#define PCM_MODE1 (1 << 4)
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#define PCM_MODE2 (2 << 4)
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#define PCM_MODE_MASK (3 << 4)
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#define PCM_BIT_ORDER (1 << 3)
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#define MCK_SCLK_64FS (0 << 0)
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#define MCK_SCLK_MCLK (2 << 0)
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#define MCK_SCLK_PREMCLK (3 << 0)
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/* CS42L73_xSPMMCC */
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#define MS_MASTER (1 << 7)
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/* CS42L73_DMMCC */
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#define MCLKDIS (1 << 0)
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#define MCLKSEL_MCLK2 (1 << 4)
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#define MCLKSEL_MCLK1 (0 << 4)
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/* CS42L73 MCLK derived from MCLK1 or MCLK2 */
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#define CS42L73_CLKID_MCLK1 0
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#define CS42L73_CLKID_MCLK2 1
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#define CS42L73_MCLKXDIV 0
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#define CS42L73_MMCCDIV 1
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#define CS42L73_XSP 0
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#define CS42L73_ASP 1
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#define CS42L73_VSP 2
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/* IS1, IM1 */
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#define MIC2_SDET (1 << 6)
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#define THMOVLD (1 << 4)
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#define DIGMIXOVFL (1 << 3)
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#define IPBOVFL (1 << 1)
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#define IPAOVFL (1 << 0)
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/* Analog Softramp */
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#define ANLGOSFT (1 << 0)
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/* HP A/B Analog Mute */
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#define HPA_MUTE (1 << 7)
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/* LO A/B Analog Mute */
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#define LOA_MUTE (1 << 7)
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/* Digital Mute */
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#define HLAD_MUTE (1 << 0)
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#define HLBD_MUTE (1 << 1)
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#define SPKD_MUTE (1 << 2)
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#define ESLD_MUTE (1 << 3)
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/* Misc defines for codec */
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#define CS42L73_RESET_GPIO 143
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#define CS42L73_DEVID 0x00042A73
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#define CS42L73_MCLKX_MIN 5644800
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#define CS42L73_MCLKX_MAX 38400000
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#define CS42L73_SPC(id) (CS42L73_XSPC + (id << 1))
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#define CS42L73_MMCC(id) (CS42L73_XSPMMCC + (id << 1))
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#define CS42L73_SPFS(id) ((id == CS42L73_ASP) ? CS42L73_ASPC : CS42L73_VXSPFS)
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#endif /* __CS42L73_H__ */
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