f7883d12a8
Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
30 lines
1.2 KiB
Plaintext
30 lines
1.2 KiB
Plaintext
What: /sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present
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What: /sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present
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What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present
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What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present
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What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present
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What: /sys/bus/iio/devices/iio:deviceX/vcxo_clk_present
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KernelVersion: 3.4.0
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Contact: linux-iio@vger.kernel.org
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Description:
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Reading returns either '1' or '0'.
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'1' means that the clock in question is present.
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'0' means that the clock is missing.
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What: /sys/bus/iio/devices/iio:deviceX/pllY_locked
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KernelVersion: 3.4.0
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Contact: linux-iio@vger.kernel.org
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Description:
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Reading returns either '1' or '0'. '1' means that the
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pllY is locked.
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What: /sys/bus/iio/devices/iio:deviceX/sync_dividers
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KernelVersion: 3.4.0
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Contact: linux-iio@vger.kernel.org
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Description:
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Writing '1' triggers the clock distribution synchronization
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functionality. All dividers are reset and the channels start
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with their predefined phase offsets (out_altvoltageY_phase).
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Writing this file has the effect as driving the external
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/SYNC pin low.
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