![Stephen Rothwell](/assets/img/avatar_default.png)
resource_size_t is 64 bits on PowerPC 64. Gets rid of this warning: arch/powerpc/kernel/pci_64.c: In function 'pcibios_map_io_space': arch/powerpc/kernel/pci_64.c:504: warning: format '%016lx' expects type 'long unsigned int', but argument 2 has type 'resource_size_t' Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
597 lines
16 KiB
C
597 lines
16 KiB
C
/*
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* Port for PPC64 David Engebretsen, IBM Corp.
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* Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
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*
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* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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* Rework, based on alpha PCI code.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <linux/list.h>
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#include <linux/syscalls.h>
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#include <linux/irq.h>
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#include <linux/vmalloc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/byteorder.h>
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#include <asm/machdep.h>
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#include <asm/ppc-pci.h>
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unsigned long pci_probe_only = 1;
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/* pci_io_base -- the base address from which io bars are offsets.
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* This is the lowest I/O base address (so bar values are always positive),
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* and it *must* be the start of ISA space if an ISA bus exists because
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* ISA drivers use hard coded offsets. If no ISA bus exists nothing
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* is mapped on the first 64K of IO space
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*/
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unsigned long pci_io_base = ISA_IO_BASE;
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EXPORT_SYMBOL(pci_io_base);
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static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
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{
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const u32 *prop;
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int len;
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prop = of_get_property(np, name, &len);
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if (prop && len >= 4)
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return *prop;
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return def;
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}
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static unsigned int pci_parse_of_flags(u32 addr0, int bridge)
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{
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unsigned int flags = 0;
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if (addr0 & 0x02000000) {
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flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
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flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
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flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
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if (addr0 & 0x40000000)
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flags |= IORESOURCE_PREFETCH
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| PCI_BASE_ADDRESS_MEM_PREFETCH;
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/* Note: We don't know whether the ROM has been left enabled
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* by the firmware or not. We mark it as disabled (ie, we do
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* not set the IORESOURCE_ROM_ENABLE flag) for now rather than
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* do a config space read, it will be force-enabled if needed
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*/
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if (!bridge && (addr0 & 0xff) == 0x30)
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flags |= IORESOURCE_READONLY;
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} else if (addr0 & 0x01000000)
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flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
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if (flags)
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flags |= IORESOURCE_SIZEALIGN;
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return flags;
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}
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static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
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{
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u64 base, size;
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unsigned int flags;
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struct resource *res;
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const u32 *addrs;
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u32 i;
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int proplen;
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addrs = of_get_property(node, "assigned-addresses", &proplen);
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if (!addrs)
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return;
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pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
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for (; proplen >= 20; proplen -= 20, addrs += 5) {
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flags = pci_parse_of_flags(addrs[0], 0);
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if (!flags)
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continue;
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base = of_read_number(&addrs[1], 2);
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size = of_read_number(&addrs[3], 2);
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if (!size)
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continue;
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i = addrs[0] & 0xff;
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pr_debug(" base: %llx, size: %llx, i: %x\n",
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(unsigned long long)base,
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(unsigned long long)size, i);
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if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
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res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
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} else if (i == dev->rom_base_reg) {
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res = &dev->resource[PCI_ROM_RESOURCE];
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flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
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} else {
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printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
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continue;
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}
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res->start = base;
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res->end = base + size - 1;
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res->flags = flags;
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res->name = pci_name(dev);
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}
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}
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struct pci_dev *of_create_pci_dev(struct device_node *node,
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struct pci_bus *bus, int devfn)
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{
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struct pci_dev *dev;
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const char *type;
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dev = alloc_pci_dev();
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if (!dev)
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return NULL;
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type = of_get_property(node, "device_type", NULL);
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if (type == NULL)
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type = "";
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pr_debug(" create device, devfn: %x, type: %s\n", devfn, type);
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dev->bus = bus;
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dev->sysdata = node;
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dev->dev.parent = bus->bridge;
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dev->dev.bus = &pci_bus_type;
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dev->devfn = devfn;
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dev->multifunction = 0; /* maybe a lie? */
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dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
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dev->device = get_int_prop(node, "device-id", 0xffff);
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dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
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dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
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dev->cfg_size = pci_cfg_space_size(dev);
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dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
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dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
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dev->class = get_int_prop(node, "class-code", 0);
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dev->revision = get_int_prop(node, "revision-id", 0);
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pr_debug(" class: 0x%x\n", dev->class);
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pr_debug(" revision: 0x%x\n", dev->revision);
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dev->current_state = 4; /* unknown power state */
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dev->error_state = pci_channel_io_normal;
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dev->dma_mask = 0xffffffff;
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if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
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/* a PCI-PCI bridge */
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dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
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dev->rom_base_reg = PCI_ROM_ADDRESS1;
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} else if (!strcmp(type, "cardbus")) {
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dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
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} else {
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dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
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dev->rom_base_reg = PCI_ROM_ADDRESS;
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/* Maybe do a default OF mapping here */
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dev->irq = NO_IRQ;
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}
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pci_parse_of_addrs(node, dev);
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pr_debug(" adding to system ...\n");
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pci_device_add(dev, bus);
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return dev;
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}
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EXPORT_SYMBOL(of_create_pci_dev);
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static void __devinit __of_scan_bus(struct device_node *node,
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struct pci_bus *bus, int rescan_existing)
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{
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struct device_node *child;
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const u32 *reg;
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int reglen, devfn;
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struct pci_dev *dev;
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pr_debug("of_scan_bus(%s) bus no %d... \n",
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node->full_name, bus->number);
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/* Scan direct children */
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for_each_child_of_node(node, child) {
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pr_debug(" * %s\n", child->full_name);
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reg = of_get_property(child, "reg", ®len);
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if (reg == NULL || reglen < 20)
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continue;
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devfn = (reg[0] >> 8) & 0xff;
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/* create a new pci_dev for this device */
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dev = of_create_pci_dev(child, bus, devfn);
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if (!dev)
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continue;
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pr_debug(" dev header type: %x\n", dev->hdr_type);
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}
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/* Apply all fixups necessary. We don't fixup the bus "self"
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* for an existing bridge that is being rescanned
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*/
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if (!rescan_existing)
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pcibios_setup_bus_self(bus);
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pcibios_setup_bus_devices(bus);
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/* Now scan child busses */
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list_for_each_entry(dev, &bus->devices, bus_list) {
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if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
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dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
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struct device_node *child = pci_device_to_OF_node(dev);
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if (dev)
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of_scan_pci_bridge(child, dev);
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}
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}
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}
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void __devinit of_scan_bus(struct device_node *node,
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struct pci_bus *bus)
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{
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__of_scan_bus(node, bus, 0);
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}
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EXPORT_SYMBOL_GPL(of_scan_bus);
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void __devinit of_rescan_bus(struct device_node *node,
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struct pci_bus *bus)
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{
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__of_scan_bus(node, bus, 1);
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}
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EXPORT_SYMBOL_GPL(of_rescan_bus);
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void __devinit of_scan_pci_bridge(struct device_node *node,
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struct pci_dev *dev)
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{
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struct pci_bus *bus;
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const u32 *busrange, *ranges;
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int len, i, mode;
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struct resource *res;
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unsigned int flags;
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u64 size;
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pr_debug("of_scan_pci_bridge(%s)\n", node->full_name);
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/* parse bus-range property */
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busrange = of_get_property(node, "bus-range", &len);
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if (busrange == NULL || len != 8) {
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printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
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node->full_name);
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return;
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}
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ranges = of_get_property(node, "ranges", &len);
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if (ranges == NULL) {
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printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
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node->full_name);
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return;
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}
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bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
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if (!bus) {
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printk(KERN_ERR "Failed to create pci bus for %s\n",
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node->full_name);
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return;
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}
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bus->primary = dev->bus->number;
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bus->subordinate = busrange[1];
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bus->bridge_ctl = 0;
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bus->sysdata = node;
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/* parse ranges property */
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/* PCI #address-cells == 3 and #size-cells == 2 always */
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res = &dev->resource[PCI_BRIDGE_RESOURCES];
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for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
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res->flags = 0;
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bus->resource[i] = res;
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++res;
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}
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i = 1;
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for (; len >= 32; len -= 32, ranges += 8) {
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flags = pci_parse_of_flags(ranges[0], 1);
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size = of_read_number(&ranges[6], 2);
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if (flags == 0 || size == 0)
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continue;
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if (flags & IORESOURCE_IO) {
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res = bus->resource[0];
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if (res->flags) {
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printk(KERN_ERR "PCI: ignoring extra I/O range"
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" for bridge %s\n", node->full_name);
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continue;
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}
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} else {
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if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
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printk(KERN_ERR "PCI: too many memory ranges"
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" for bridge %s\n", node->full_name);
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continue;
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}
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res = bus->resource[i];
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++i;
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}
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res->start = of_read_number(&ranges[1], 2);
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res->end = res->start + size - 1;
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res->flags = flags;
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}
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sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
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bus->number);
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pr_debug(" bus name: %s\n", bus->name);
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mode = PCI_PROBE_NORMAL;
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if (ppc_md.pci_probe_mode)
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mode = ppc_md.pci_probe_mode(bus);
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pr_debug(" probe mode: %d\n", mode);
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if (mode == PCI_PROBE_DEVTREE)
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of_scan_bus(node, bus);
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else if (mode == PCI_PROBE_NORMAL)
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pci_scan_child_bus(bus);
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}
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EXPORT_SYMBOL(of_scan_pci_bridge);
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void __devinit scan_phb(struct pci_controller *hose)
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{
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struct pci_bus *bus;
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struct device_node *node = hose->dn;
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int mode;
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pr_debug("PCI: Scanning PHB %s\n",
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node ? node->full_name : "<NO NAME>");
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/* Create an empty bus for the toplevel */
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bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
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if (bus == NULL) {
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printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
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hose->global_number);
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return;
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}
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bus->secondary = hose->first_busno;
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hose->bus = bus;
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/* Get some IO space for the new PHB */
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pcibios_map_io_space(bus);
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/* Wire up PHB bus resources */
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pcibios_setup_phb_resources(hose);
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/* Get probe mode and perform scan */
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mode = PCI_PROBE_NORMAL;
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if (node && ppc_md.pci_probe_mode)
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mode = ppc_md.pci_probe_mode(bus);
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pr_debug(" probe mode: %d\n", mode);
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if (mode == PCI_PROBE_DEVTREE) {
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bus->subordinate = hose->last_busno;
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of_scan_bus(node, bus);
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}
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if (mode == PCI_PROBE_NORMAL)
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hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
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}
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose, *tmp;
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printk(KERN_INFO "PCI: Probing PCI hardware\n");
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/* For now, override phys_mem_access_prot. If we need it,g
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* later, we may move that initialization to each ppc_md
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*/
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ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
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if (pci_probe_only)
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ppc_pci_flags |= PPC_PCI_PROBE_ONLY;
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/* On ppc64, we always enable PCI domains and we keep domain 0
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* backward compatible in /proc for video cards
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*/
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ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;
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/* Scan all of the recorded PCI controllers. */
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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scan_phb(hose);
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pci_bus_add_devices(hose->bus);
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}
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/* Call common code to handle resource allocation */
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pcibios_resource_survey();
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printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
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return 0;
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}
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subsys_initcall(pcibios_init);
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#ifdef CONFIG_HOTPLUG
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int pcibios_unmap_io_space(struct pci_bus *bus)
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{
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struct pci_controller *hose;
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WARN_ON(bus == NULL);
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/* If this is not a PHB, we only flush the hash table over
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* the area mapped by this bridge. We don't play with the PTE
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* mappings since we might have to deal with sub-page alignemnts
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* so flushing the hash table is the only sane way to make sure
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* that no hash entries are covering that removed bridge area
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* while still allowing other busses overlapping those pages
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*
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* Note: If we ever support P2P hotplug on Book3E, we'll have
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* to do an appropriate TLB flush here too
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*/
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if (bus->self) {
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struct resource *res = bus->resource[0];
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pr_debug("IO unmapping for PCI-PCI bridge %s\n",
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pci_name(bus->self));
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#ifdef CONFIG_PPC_STD_MMU_64
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__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
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res->end + _IO_BASE + 1);
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#endif
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return 0;
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}
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/* Get the host bridge */
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hose = pci_bus_to_host(bus);
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/* Check if we have IOs allocated */
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if (hose->io_base_alloc == 0)
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return 0;
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pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
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pr_debug(" alloc=0x%p\n", hose->io_base_alloc);
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/* This is a PHB, we fully unmap the IO area */
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vunmap(hose->io_base_alloc);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
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#endif /* CONFIG_HOTPLUG */
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int __devinit pcibios_map_io_space(struct pci_bus *bus)
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{
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struct vm_struct *area;
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unsigned long phys_page;
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unsigned long size_page;
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unsigned long io_virt_offset;
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struct pci_controller *hose;
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WARN_ON(bus == NULL);
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/* If this not a PHB, nothing to do, page tables still exist and
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* thus HPTEs will be faulted in when needed
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*/
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if (bus->self) {
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pr_debug("IO mapping for PCI-PCI bridge %s\n",
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pci_name(bus->self));
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pr_debug(" virt=0x%016llx...0x%016llx\n",
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bus->resource[0]->start + _IO_BASE,
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bus->resource[0]->end + _IO_BASE);
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return 0;
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}
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/* Get the host bridge */
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hose = pci_bus_to_host(bus);
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phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
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|
size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
|
|
|
|
/* Make sure IO area address is clear */
|
|
hose->io_base_alloc = NULL;
|
|
|
|
/* If there's no IO to map on that bus, get away too */
|
|
if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
|
|
return 0;
|
|
|
|
/* Let's allocate some IO space for that guy. We don't pass
|
|
* VM_IOREMAP because we don't care about alignment tricks that
|
|
* the core does in that case. Maybe we should due to stupid card
|
|
* with incomplete address decoding but I'd rather not deal with
|
|
* those outside of the reserved 64K legacy region.
|
|
*/
|
|
area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
|
|
if (area == NULL)
|
|
return -ENOMEM;
|
|
hose->io_base_alloc = area->addr;
|
|
hose->io_base_virt = (void __iomem *)(area->addr +
|
|
hose->io_base_phys - phys_page);
|
|
|
|
pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
|
|
pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
|
|
hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
|
|
pr_debug(" size=0x%016llx (alloc=0x%016lx)\n",
|
|
hose->pci_io_size, size_page);
|
|
|
|
/* Establish the mapping */
|
|
if (__ioremap_at(phys_page, area->addr, size_page,
|
|
_PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
|
|
return -ENOMEM;
|
|
|
|
/* Fixup hose IO resource */
|
|
io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
|
|
hose->io_resource.start += io_virt_offset;
|
|
hose->io_resource.end += io_virt_offset;
|
|
|
|
pr_debug(" hose->io_resource=0x%016llx...0x%016llx\n",
|
|
hose->io_resource.start, hose->io_resource.end);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pcibios_map_io_space);
|
|
|
|
#define IOBASE_BRIDGE_NUMBER 0
|
|
#define IOBASE_MEMORY 1
|
|
#define IOBASE_IO 2
|
|
#define IOBASE_ISA_IO 3
|
|
#define IOBASE_ISA_MEM 4
|
|
|
|
long sys_pciconfig_iobase(long which, unsigned long in_bus,
|
|
unsigned long in_devfn)
|
|
{
|
|
struct pci_controller* hose;
|
|
struct list_head *ln;
|
|
struct pci_bus *bus = NULL;
|
|
struct device_node *hose_node;
|
|
|
|
/* Argh ! Please forgive me for that hack, but that's the
|
|
* simplest way to get existing XFree to not lockup on some
|
|
* G5 machines... So when something asks for bus 0 io base
|
|
* (bus 0 is HT root), we return the AGP one instead.
|
|
*/
|
|
if (in_bus == 0 && machine_is_compatible("MacRISC4")) {
|
|
struct device_node *agp;
|
|
|
|
agp = of_find_compatible_node(NULL, NULL, "u3-agp");
|
|
if (agp)
|
|
in_bus = 0xf0;
|
|
of_node_put(agp);
|
|
}
|
|
|
|
/* That syscall isn't quite compatible with PCI domains, but it's
|
|
* used on pre-domains setup. We return the first match
|
|
*/
|
|
|
|
for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
|
|
bus = pci_bus_b(ln);
|
|
if (in_bus >= bus->number && in_bus <= bus->subordinate)
|
|
break;
|
|
bus = NULL;
|
|
}
|
|
if (bus == NULL || bus->sysdata == NULL)
|
|
return -ENODEV;
|
|
|
|
hose_node = (struct device_node *)bus->sysdata;
|
|
hose = PCI_DN(hose_node)->phb;
|
|
|
|
switch (which) {
|
|
case IOBASE_BRIDGE_NUMBER:
|
|
return (long)hose->first_busno;
|
|
case IOBASE_MEMORY:
|
|
return (long)hose->pci_mem_offset;
|
|
case IOBASE_IO:
|
|
return (long)hose->io_base_phys;
|
|
case IOBASE_ISA_IO:
|
|
return (long)isa_io_base;
|
|
case IOBASE_ISA_MEM:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
#ifdef CONFIG_NUMA
|
|
int pcibus_to_node(struct pci_bus *bus)
|
|
{
|
|
struct pci_controller *phb = pci_bus_to_host(bus);
|
|
return phb->node;
|
|
}
|
|
EXPORT_SYMBOL(pcibus_to_node);
|
|
#endif
|