f99fb607fb
Setup the cpu_logical_map during boot. Moreover, every SBI call and PLIC context are based on the physical hartid. Use the logical CPU to hartid mapping to pass correct hartid to respective functions. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
132 lines
3.2 KiB
C
132 lines
3.2 KiB
C
/*
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* SMP initialisation and IPI support
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* Based on arch/arm64/kernel/smp.c
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2015 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/percpu.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/sched/task_stack.h>
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#include <linux/sched/mm.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/sections.h>
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#include <asm/sbi.h>
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void *__cpu_up_stack_pointer[NR_CPUS];
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void *__cpu_up_task_pointer[NR_CPUS];
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void __init smp_prepare_boot_cpu(void)
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{
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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}
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void __init setup_smp(void)
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{
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struct device_node *dn = NULL;
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int hart;
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bool found_boot_cpu = false;
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int cpuid = 1;
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while ((dn = of_find_node_by_type(dn, "cpu"))) {
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hart = riscv_of_processor_hartid(dn);
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if (hart < 0)
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continue;
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if (hart == cpuid_to_hartid_map(0)) {
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BUG_ON(found_boot_cpu);
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found_boot_cpu = 1;
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continue;
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}
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cpuid_to_hartid_map(cpuid) = hart;
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set_cpu_possible(cpuid, true);
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set_cpu_present(cpuid, true);
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cpuid++;
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}
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BUG_ON(!found_boot_cpu);
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}
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int __cpu_up(unsigned int cpu, struct task_struct *tidle)
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{
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int hartid = cpuid_to_hartid_map(cpu);
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tidle->thread_info.cpu = cpu;
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/*
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* On RISC-V systems, all harts boot on their own accord. Our _start
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* selects the first hart to boot the kernel and causes the remainder
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* of the harts to spin in a loop waiting for their stack pointer to be
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* setup by that main hart. Writing __cpu_up_stack_pointer signals to
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* the spinning harts that they can continue the boot process.
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*/
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smp_mb();
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WRITE_ONCE(__cpu_up_stack_pointer[hartid],
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task_stack_page(tidle) + THREAD_SIZE);
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WRITE_ONCE(__cpu_up_task_pointer[hartid], tidle);
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while (!cpu_online(cpu))
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cpu_relax();
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return 0;
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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}
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/*
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* C entry point for a secondary processor.
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*/
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asmlinkage void __init smp_callin(void)
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{
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struct mm_struct *mm = &init_mm;
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/* All kernel threads share the same mm context. */
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mmgrab(mm);
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current->active_mm = mm;
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trap_init();
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notify_cpu_starting(smp_processor_id());
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set_cpu_online(smp_processor_id(), 1);
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/*
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* Remote TLB flushes are ignored while the CPU is offline, so emit
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* a local TLB flush right now just in case.
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*/
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local_flush_tlb_all();
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/*
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* Disable preemption before enabling interrupts, so we don't try to
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* schedule a CPU that hasn't actually started yet.
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*/
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preempt_disable();
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local_irq_enable();
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cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
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}
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