65c0118453
* This patch replaces the dangerous lvalue version of cpumask_of_cpu
with new cpumask_of_cpu_ptr macros. These are patterned after the
node_to_cpumask_ptr macros.
In general terms, if there is a cpumask_of_cpu_map[] then a pointer to
the cpumask_of_cpu_map[cpu] entry is used. The cpumask_of_cpu_map
is provided when there is a large NR_CPUS count, reducing
greatly the amount of code generated and stack space used for
cpumask_of_cpu(). The pointer to the cpumask_t value is needed for
calling set_cpus_allowed_ptr() to reduce the amount of stack space
needed to pass the cpumask_t value.
If there isn't a cpumask_of_cpu_map[], then a temporary variable is
declared and filled in with value from cpumask_of_cpu(cpu) as well as
a pointer variable pointing to this temporary variable. Afterwards,
the pointer is used to reference the cpumask value. The compiler
will optimize out the extra dereference through the pointer as well
as the stack space used for the pointer, resulting in identical code.
A good example of the orthogonal usages is in net/sunrpc/svc.c:
case SVC_POOL_PERCPU:
{
unsigned int cpu = m->pool_to[pidx];
cpumask_of_cpu_ptr(cpumask, cpu);
*oldmask = current->cpus_allowed;
set_cpus_allowed_ptr(current, cpumask);
return 1;
}
case SVC_POOL_PERNODE:
{
unsigned int node = m->pool_to[pidx];
node_to_cpumask_ptr(nodecpumask, node);
*oldmask = current->cpus_allowed;
set_cpus_allowed_ptr(current, nodecpumask);
return 1;
}
Signed-off-by: Mike Travis <travis@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
166 lines
4.4 KiB
C
166 lines
4.4 KiB
C
/*
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* Copyright (C) 2005 Intel Corporation
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* Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
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* - Added _PDC for SMP C-states on Intel CPUs
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <linux/cpu.h>
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#include <linux/sched.h>
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#include <acpi/processor.h>
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#include <asm/acpi.h>
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/*
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* Initialize bm_flags based on the CPU cache properties
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* On SMP it depends on cache configuration
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* - When cache is not shared among all CPUs, we flush cache
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* before entering C3.
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* - When cache is shared among all CPUs, we use bm_check
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* mechanism as in UP case
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*
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* This routine is called only after all the CPUs are online
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*/
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void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
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unsigned int cpu)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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flags->bm_check = 0;
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if (num_online_cpus() == 1)
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flags->bm_check = 1;
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else if (c->x86_vendor == X86_VENDOR_INTEL) {
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/*
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* Today all CPUs that support C3 share cache.
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* TBD: This needs to look at cache shared map, once
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* multi-core detection patch makes to the base.
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*/
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flags->bm_check = 1;
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}
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}
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EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
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/* The code below handles cstate entry with monitor-mwait pair on Intel*/
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struct cstate_entry {
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struct {
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unsigned int eax;
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unsigned int ecx;
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} states[ACPI_PROCESSOR_MAX_POWER];
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};
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static struct cstate_entry *cpu_cstate_entry; /* per CPU ptr */
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static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
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#define MWAIT_SUBSTATE_MASK (0xf)
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#define MWAIT_SUBSTATE_SIZE (4)
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#define CPUID_MWAIT_LEAF (5)
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#define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
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#define CPUID5_ECX_INTERRUPT_BREAK (0x2)
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#define MWAIT_ECX_INTERRUPT_BREAK (0x1)
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#define NATIVE_CSTATE_BEYOND_HALT (2)
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int acpi_processor_ffh_cstate_probe(unsigned int cpu,
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struct acpi_processor_cx *cx, struct acpi_power_register *reg)
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{
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struct cstate_entry *percpu_entry;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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cpumask_t saved_mask;
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cpumask_of_cpu_ptr(new_mask, cpu);
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int retval;
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unsigned int eax, ebx, ecx, edx;
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unsigned int edx_part;
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unsigned int cstate_type; /* C-state type and not ACPI C-state type */
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unsigned int num_cstate_subtype;
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if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF )
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return -1;
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if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
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return -1;
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percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
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percpu_entry->states[cx->index].eax = 0;
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percpu_entry->states[cx->index].ecx = 0;
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/* Make sure we are running on right CPU */
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saved_mask = current->cpus_allowed;
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retval = set_cpus_allowed_ptr(current, new_mask);
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if (retval)
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return -1;
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cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
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/* Check whether this particular cx_type (in CST) is supported or not */
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cstate_type = (cx->address >> MWAIT_SUBSTATE_SIZE) + 1;
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edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
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num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
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retval = 0;
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if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
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retval = -1;
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goto out;
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}
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/* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
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if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
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!(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
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retval = -1;
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goto out;
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}
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percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
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/* Use the hint in CST */
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percpu_entry->states[cx->index].eax = cx->address;
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if (!mwait_supported[cstate_type]) {
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mwait_supported[cstate_type] = 1;
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printk(KERN_DEBUG "Monitor-Mwait will be used to enter C-%d "
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"state\n", cx->type);
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}
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snprintf(cx->desc, ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x",
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cx->address);
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out:
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set_cpus_allowed_ptr(current, &saved_mask);
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return retval;
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}
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EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
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void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
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{
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unsigned int cpu = smp_processor_id();
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struct cstate_entry *percpu_entry;
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percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
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mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
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percpu_entry->states[cx->index].ecx);
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}
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EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
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static int __init ffh_cstate_init(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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if (c->x86_vendor != X86_VENDOR_INTEL)
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return -1;
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cpu_cstate_entry = alloc_percpu(struct cstate_entry);
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return 0;
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}
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static void __exit ffh_cstate_exit(void)
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{
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free_percpu(cpu_cstate_entry);
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cpu_cstate_entry = NULL;
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}
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arch_initcall(ffh_cstate_init);
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__exitcall(ffh_cstate_exit);
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