9447332ffa
The 35h instruction op code has two aliases/macro definitions: - SPINOR_OP_RDCR from include/linux/mtd/spi-nor.h - SPINOR_OP_RDSR2 from drivers/mtd/devices/serial_flash_cmds.h Actually, some manufacturers name the associated internal register Status Register 2 whereas other manufacturers name it Configuration Register hence the two different macros for the very same instruction op code. Since the spi-nor.h file is the reference file for all SPI NOR instruction op codes, this patch removes the definition of the SPINOR_OP_RDSR2 macro. Also the SPINOR_OP_RDSR2 macro will be associated to another instruction op code in a further patch so we need to avoid a conflict defining this macro twice. Indeed the JESD216 rev B specification, defining the SFDP tables, also refers to the 3Eh and 3Fh instruction op codes to write/read the Status Register 2 on some SPI NOR flash memories, the 35h op code still being used to read the Configuration Register/Status Register 2 on other memories. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
54 lines
1.8 KiB
C
54 lines
1.8 KiB
C
/*
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* Generic/SFDP Flash Commands and Device Capabilities
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*
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* Copyright (C) 2013 Lee Jones <lee.jones@lianro.org>
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*
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef _MTD_SERIAL_FLASH_CMDS_H
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#define _MTD_SERIAL_FLASH_CMDS_H
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/* Generic Flash Commands/OPCODEs */
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#define SPINOR_OP_WRVCR 0x81
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#define SPINOR_OP_RDVCR 0x85
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/* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
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#define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */
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#define SPINOR_OP_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
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#define SPINOR_OP_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
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#define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
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#define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
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/* Configuration flags */
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#define FLASH_FLAG_SINGLE 0x000000ff
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#define FLASH_FLAG_READ_WRITE 0x00000001
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#define FLASH_FLAG_READ_FAST 0x00000002
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#define FLASH_FLAG_SE_4K 0x00000004
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#define FLASH_FLAG_SE_32K 0x00000008
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#define FLASH_FLAG_CE 0x00000010
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#define FLASH_FLAG_32BIT_ADDR 0x00000020
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#define FLASH_FLAG_RESET 0x00000040
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#define FLASH_FLAG_DYB_LOCKING 0x00000080
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#define FLASH_FLAG_DUAL 0x0000ff00
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#define FLASH_FLAG_READ_1_1_2 0x00000100
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#define FLASH_FLAG_READ_1_2_2 0x00000200
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#define FLASH_FLAG_READ_2_2_2 0x00000400
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#define FLASH_FLAG_WRITE_1_1_2 0x00001000
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#define FLASH_FLAG_WRITE_1_2_2 0x00002000
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#define FLASH_FLAG_WRITE_2_2_2 0x00004000
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#define FLASH_FLAG_QUAD 0x00ff0000
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#define FLASH_FLAG_READ_1_1_4 0x00010000
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#define FLASH_FLAG_READ_1_4_4 0x00020000
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#define FLASH_FLAG_READ_4_4_4 0x00040000
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#define FLASH_FLAG_WRITE_1_1_4 0x00100000
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#define FLASH_FLAG_WRITE_1_4_4 0x00200000
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#define FLASH_FLAG_WRITE_4_4_4 0x00400000
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#endif /* _MTD_SERIAL_FLASH_CMDS_H */
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