257 lines
7.0 KiB
C
257 lines
7.0 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2016 Intel Corporation
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*/
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#ifndef __I915_GEM_OBJECT_TYPES_H__
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#define __I915_GEM_OBJECT_TYPES_H__
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#include <drm/drm_gem.h>
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#include "i915_active.h"
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#include "i915_selftest.h"
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struct drm_i915_gem_object;
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struct intel_fronbuffer;
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/*
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* struct i915_lut_handle tracks the fast lookups from handle to vma used
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* for execbuf. Although we use a radixtree for that mapping, in order to
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* remove them as the object or context is closed, we need a secondary list
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* and a translation entry (i915_lut_handle).
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*/
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struct i915_lut_handle {
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struct list_head obj_link;
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struct i915_gem_context *ctx;
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u32 handle;
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};
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struct drm_i915_gem_object_ops {
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unsigned int flags;
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#define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
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#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
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#define I915_GEM_OBJECT_IS_PROXY BIT(2)
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#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(3)
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/* Interface between the GEM object and its backing storage.
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* get_pages() is called once prior to the use of the associated set
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* of pages before to binding them into the GTT, and put_pages() is
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* called after we no longer need them. As we expect there to be
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* associated cost with migrating pages between the backing storage
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* and making them available for the GPU (e.g. clflush), we may hold
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* onto the pages after they are no longer referenced by the GPU
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* in case they may be used again shortly (for example migrating the
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* pages to a different memory domain within the GTT). put_pages()
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* will therefore most likely be called when the object itself is
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* being released or under memory pressure (where we attempt to
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* reap pages for the shrinker).
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*/
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int (*get_pages)(struct drm_i915_gem_object *obj);
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void (*put_pages)(struct drm_i915_gem_object *obj,
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struct sg_table *pages);
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void (*truncate)(struct drm_i915_gem_object *obj);
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void (*writeback)(struct drm_i915_gem_object *obj);
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int (*pwrite)(struct drm_i915_gem_object *obj,
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const struct drm_i915_gem_pwrite *arg);
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int (*dmabuf_export)(struct drm_i915_gem_object *obj);
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void (*release)(struct drm_i915_gem_object *obj);
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};
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struct drm_i915_gem_object {
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struct drm_gem_object base;
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const struct drm_i915_gem_object_ops *ops;
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struct {
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/**
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* @vma.lock: protect the list/tree of vmas
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*/
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spinlock_t lock;
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/**
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* @vma.list: List of VMAs backed by this object
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*
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* The VMA on this list are ordered by type, all GGTT vma are
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* placed at the head and all ppGTT vma are placed at the tail.
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* The different types of GGTT vma are unordered between
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* themselves, use the @vma.tree (which has a defined order
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* between all VMA) to quickly find an exact match.
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*/
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struct list_head list;
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/**
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* @vma.tree: Ordered tree of VMAs backed by this object
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*
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* All VMA created for this object are placed in the @vma.tree
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* for fast retrieval via a binary search in
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* i915_vma_instance(). They are also added to @vma.list for
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* easy iteration.
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*/
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struct rb_root tree;
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} vma;
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/**
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* @lut_list: List of vma lookup entries in use for this object.
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*
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* If this object is closed, we need to remove all of its VMA from
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* the fast lookup index in associated contexts; @lut_list provides
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* this translation from object to context->handles_vma.
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*/
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struct list_head lut_list;
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/** Stolen memory for this object, instead of being backed by shmem. */
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struct drm_mm_node *stolen;
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union {
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struct rcu_head rcu;
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struct llist_node freed;
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};
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/**
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* Whether the object is currently in the GGTT mmap.
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*/
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unsigned int userfault_count;
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struct list_head userfault_link;
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I915_SELFTEST_DECLARE(struct list_head st_link);
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/*
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* Is the object to be mapped as read-only to the GPU
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* Only honoured if hardware has relevant pte bit
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*/
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unsigned int cache_level:3;
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unsigned int cache_coherent:2;
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#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
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#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
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unsigned int cache_dirty:1;
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/**
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* @read_domains: Read memory domains.
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*
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* These monitor which caches contain read/write data related to the
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* object. When transitioning from one set of domains to another,
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* the driver is called to ensure that caches are suitably flushed and
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* invalidated.
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*/
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u16 read_domains;
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/**
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* @write_domain: Corresponding unique write memory domain.
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*/
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u16 write_domain;
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struct intel_frontbuffer *frontbuffer;
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/** Current tiling stride for the object, if it's tiled. */
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unsigned int tiling_and_stride;
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#define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
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#define TILING_MASK (FENCE_MINIMUM_STRIDE - 1)
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#define STRIDE_MASK (~TILING_MASK)
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/** Count of VMA actually bound by this object */
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atomic_t bind_count;
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/** Count of how many global VMA are currently pinned for use by HW */
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unsigned int pin_global;
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struct {
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struct mutex lock; /* protects the pages and their use */
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atomic_t pages_pin_count;
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struct sg_table *pages;
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void *mapping;
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/* TODO: whack some of this into the error state */
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struct i915_page_sizes {
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/**
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* The sg mask of the pages sg_table. i.e the mask of
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* of the lengths for each sg entry.
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*/
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unsigned int phys;
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/**
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* The gtt page sizes we are allowed to use given the
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* sg mask and the supported page sizes. This will
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* express the smallest unit we can use for the whole
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* object, as well as the larger sizes we may be able
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* to use opportunistically.
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*/
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unsigned int sg;
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/**
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* The actual gtt page size usage. Since we can have
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* multiple vma associated with this object we need to
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* prevent any trampling of state, hence a copy of this
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* struct also lives in each vma, therefore the gtt
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* value here should only be read/write through the vma.
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*/
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unsigned int gtt;
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} page_sizes;
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I915_SELFTEST_DECLARE(unsigned int page_mask);
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struct i915_gem_object_page_iter {
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struct scatterlist *sg_pos;
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unsigned int sg_idx; /* in pages, but 32bit eek! */
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struct radix_tree_root radix;
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struct mutex lock; /* protects this cache */
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} get_page;
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/**
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* Element within i915->mm.unbound_list or i915->mm.bound_list,
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* locked by i915->mm.obj_lock.
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*/
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struct list_head link;
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/**
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* Advice: are the backing pages purgeable?
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*/
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unsigned int madv:2;
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/**
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* This is set if the object has been written to since the
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* pages were last acquired.
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*/
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bool dirty:1;
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/**
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* This is set if the object has been pinned due to unknown
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* swizzling.
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*/
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bool quirked:1;
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} mm;
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/** Record of address bit 17 of each page at last unbind. */
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unsigned long *bit_17;
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union {
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struct i915_gem_userptr {
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uintptr_t ptr;
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struct i915_mm_struct *mm;
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struct i915_mmu_object *mmu_object;
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struct work_struct *work;
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} userptr;
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unsigned long scratch;
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void *gvt_info;
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};
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/** for phys allocated objects */
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struct drm_dma_handle *phys_handle;
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};
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static inline struct drm_i915_gem_object *
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to_intel_bo(struct drm_gem_object *gem)
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{
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/* Assert that to_intel_bo(NULL) == NULL */
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BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
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return container_of(gem, struct drm_i915_gem_object, base);
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}
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#endif
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