![Philippe Gerum](/assets/img/avatar_default.png)
Signed-off-by: Philippe Gerum <rpm@xenomai.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
1319 lines
30 KiB
C
1319 lines
30 KiB
C
/*
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* File: arch/blackfin/mach-common/ints-priority.c
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*
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* Description: Set up the interrupt priorities
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*
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* Modified:
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* 1996 Roman Zippel
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* 1999 D. Jeff Dionne <jeff@uclinux.org>
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* 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
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* 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
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* 2003 Metrowerks/Motorola
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* 2003 Bas Vermeulen <bas@buyways.nl>
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <linux/kernel_stat.h>
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#include <linux/seq_file.h>
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#include <linux/irq.h>
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#ifdef CONFIG_IPIPE
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#include <linux/ipipe.h>
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#endif
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#ifdef CONFIG_KGDB
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#include <linux/kgdb.h>
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#endif
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#include <asm/traps.h>
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#include <asm/blackfin.h>
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#include <asm/gpio.h>
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#include <asm/irq_handler.h>
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#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
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#ifdef BF537_FAMILY
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# define BF537_GENERIC_ERROR_INT_DEMUX
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#else
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# undef BF537_GENERIC_ERROR_INT_DEMUX
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#endif
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/*
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* NOTES:
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* - we have separated the physical Hardware interrupt from the
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* levels that the LINUX kernel sees (see the description in irq.h)
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* -
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*/
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#ifndef CONFIG_SMP
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/* Initialize this to an actual value to force it into the .data
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* section so that we know it is properly initialized at entry into
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* the kernel but before bss is initialized to zero (which is where
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* it would live otherwise). The 0x1f magic represents the IRQs we
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* cannot actually mask out in hardware.
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*/
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unsigned long bfin_irq_flags = 0x1f;
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EXPORT_SYMBOL(bfin_irq_flags);
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#endif
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/* The number of spurious interrupts */
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atomic_t num_spurious;
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#ifdef CONFIG_PM
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unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
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unsigned vr_wakeup;
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#endif
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struct ivgx {
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/* irq number for request_irq, available in mach-bf5xx/irq.h */
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unsigned int irqno;
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/* corresponding bit in the SIC_ISR register */
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unsigned int isrflag;
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} ivg_table[NR_PERI_INTS];
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struct ivg_slice {
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/* position of first irq in ivg_table for given ivg */
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struct ivgx *ifirst;
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struct ivgx *istop;
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} ivg7_13[IVG13 - IVG7 + 1];
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/*
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* Search SIC_IAR and fill tables with the irqvalues
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* and their positions in the SIC_ISR register.
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*/
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static void __init search_IAR(void)
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{
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unsigned ivg, irq_pos = 0;
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for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
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int irqn;
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ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
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for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
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int iar_shift = (irqn & 7) * 4;
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if (ivg == (0xf &
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#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
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|| defined(CONFIG_BF539) || defined(CONFIG_BF51x)
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bfin_read32((unsigned long *)SIC_IAR0 +
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((irqn % 32) >> 3) + ((irqn / 32) *
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((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
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#else
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bfin_read32((unsigned long *)SIC_IAR0 +
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(irqn >> 3)) >> iar_shift)) {
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#endif
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ivg_table[irq_pos].irqno = IVG7 + irqn;
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ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
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ivg7_13[ivg].istop++;
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irq_pos++;
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}
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}
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}
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}
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/*
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* This is for core internal IRQs
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*/
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static void bfin_ack_noop(unsigned int irq)
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{
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/* Dummy function. */
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}
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static void bfin_core_mask_irq(unsigned int irq)
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{
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bfin_irq_flags &= ~(1 << irq);
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if (!irqs_disabled_hw())
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local_irq_enable_hw();
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}
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static void bfin_core_unmask_irq(unsigned int irq)
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{
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bfin_irq_flags |= 1 << irq;
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/*
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* If interrupts are enabled, IMASK must contain the same value
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* as bfin_irq_flags. Make sure that invariant holds. If interrupts
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* are currently disabled we need not do anything; one of the
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* callers will take care of setting IMASK to the proper value
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* when reenabling interrupts.
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* local_irq_enable just does "STI bfin_irq_flags", so it's exactly
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* what we need.
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*/
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if (!irqs_disabled_hw())
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local_irq_enable_hw();
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return;
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}
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static void bfin_internal_mask_irq(unsigned int irq)
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{
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unsigned long flags;
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#ifdef CONFIG_BF53x
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local_irq_save_hw(flags);
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bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
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~(1 << SIC_SYSIRQ(irq)));
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#else
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unsigned mask_bank, mask_bit;
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local_irq_save_hw(flags);
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mask_bank = SIC_SYSIRQ(irq) / 32;
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mask_bit = SIC_SYSIRQ(irq) % 32;
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bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
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~(1 << mask_bit));
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#ifdef CONFIG_SMP
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bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
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~(1 << mask_bit));
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#endif
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#endif
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local_irq_restore_hw(flags);
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}
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static void bfin_internal_unmask_irq(unsigned int irq)
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{
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unsigned long flags;
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#ifdef CONFIG_BF53x
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local_irq_save_hw(flags);
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bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
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(1 << SIC_SYSIRQ(irq)));
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#else
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unsigned mask_bank, mask_bit;
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local_irq_save_hw(flags);
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mask_bank = SIC_SYSIRQ(irq) / 32;
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mask_bit = SIC_SYSIRQ(irq) % 32;
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bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
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(1 << mask_bit));
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#ifdef CONFIG_SMP
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bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
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(1 << mask_bit));
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#endif
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#endif
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local_irq_restore_hw(flags);
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}
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#ifdef CONFIG_PM
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int bfin_internal_set_wake(unsigned int irq, unsigned int state)
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{
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u32 bank, bit, wakeup = 0;
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unsigned long flags;
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bank = SIC_SYSIRQ(irq) / 32;
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bit = SIC_SYSIRQ(irq) % 32;
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switch (irq) {
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#ifdef IRQ_RTC
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case IRQ_RTC:
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wakeup |= WAKE;
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break;
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#endif
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#ifdef IRQ_CAN0_RX
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case IRQ_CAN0_RX:
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wakeup |= CANWE;
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break;
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#endif
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#ifdef IRQ_CAN1_RX
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case IRQ_CAN1_RX:
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wakeup |= CANWE;
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break;
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#endif
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#ifdef IRQ_USB_INT0
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case IRQ_USB_INT0:
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wakeup |= USBWE;
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break;
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#endif
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#ifdef IRQ_KEY
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case IRQ_KEY:
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wakeup |= KPADWE;
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break;
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#endif
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#ifdef CONFIG_BF54x
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case IRQ_CNT:
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wakeup |= ROTWE;
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break;
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#endif
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default:
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break;
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}
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local_irq_save_hw(flags);
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if (state) {
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bfin_sic_iwr[bank] |= (1 << bit);
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vr_wakeup |= wakeup;
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} else {
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bfin_sic_iwr[bank] &= ~(1 << bit);
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vr_wakeup &= ~wakeup;
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}
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local_irq_restore_hw(flags);
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return 0;
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}
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#endif
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static struct irq_chip bfin_core_irqchip = {
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.name = "CORE",
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.ack = bfin_ack_noop,
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.mask = bfin_core_mask_irq,
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.unmask = bfin_core_unmask_irq,
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};
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static struct irq_chip bfin_internal_irqchip = {
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.name = "INTN",
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.ack = bfin_ack_noop,
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.mask = bfin_internal_mask_irq,
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.unmask = bfin_internal_unmask_irq,
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.mask_ack = bfin_internal_mask_irq,
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.disable = bfin_internal_mask_irq,
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.enable = bfin_internal_unmask_irq,
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#ifdef CONFIG_PM
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.set_wake = bfin_internal_set_wake,
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#endif
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};
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static void bfin_handle_irq(unsigned irq)
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{
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#ifdef CONFIG_IPIPE
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struct pt_regs regs; /* Contents not used. */
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ipipe_trace_irq_entry(irq);
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__ipipe_handle_irq(irq, ®s);
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ipipe_trace_irq_exit(irq);
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#else /* !CONFIG_IPIPE */
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struct irq_desc *desc = irq_desc + irq;
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desc->handle_irq(irq, desc);
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#endif /* !CONFIG_IPIPE */
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}
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#ifdef BF537_GENERIC_ERROR_INT_DEMUX
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static int error_int_mask;
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static void bfin_generic_error_mask_irq(unsigned int irq)
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{
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error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
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if (!error_int_mask)
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bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
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}
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static void bfin_generic_error_unmask_irq(unsigned int irq)
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{
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bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
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error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
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}
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static struct irq_chip bfin_generic_error_irqchip = {
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.name = "ERROR",
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.ack = bfin_ack_noop,
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.mask_ack = bfin_generic_error_mask_irq,
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.mask = bfin_generic_error_mask_irq,
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.unmask = bfin_generic_error_unmask_irq,
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};
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static void bfin_demux_error_irq(unsigned int int_err_irq,
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struct irq_desc *inta_desc)
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{
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int irq = 0;
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
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if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
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irq = IRQ_MAC_ERROR;
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else
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#endif
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if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
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irq = IRQ_SPORT0_ERROR;
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else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
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irq = IRQ_SPORT1_ERROR;
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else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
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irq = IRQ_PPI_ERROR;
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else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
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irq = IRQ_CAN_ERROR;
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else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
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irq = IRQ_SPI_ERROR;
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else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
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(bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
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irq = IRQ_UART0_ERROR;
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else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
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(bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
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irq = IRQ_UART1_ERROR;
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if (irq) {
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if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
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bfin_handle_irq(irq);
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else {
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switch (irq) {
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case IRQ_PPI_ERROR:
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bfin_write_PPI_STATUS(PPI_ERR_MASK);
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break;
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
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case IRQ_MAC_ERROR:
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bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
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break;
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#endif
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case IRQ_SPORT0_ERROR:
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bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
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break;
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case IRQ_SPORT1_ERROR:
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bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
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break;
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case IRQ_CAN_ERROR:
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bfin_write_CAN_GIS(CAN_ERR_MASK);
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break;
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case IRQ_SPI_ERROR:
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bfin_write_SPI_STAT(SPI_ERR_MASK);
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break;
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default:
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break;
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}
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pr_debug("IRQ %d:"
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" MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
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irq);
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}
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} else
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printk(KERN_ERR
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"%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
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" INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
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__func__, __FILE__, __LINE__);
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}
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#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
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static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
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{
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#ifdef CONFIG_IPIPE
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_set_irq_handler(irq, handle_level_irq);
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#else
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struct irq_desc *desc = irq_desc + irq;
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/* May not call generic set_irq_handler() due to spinlock
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recursion. */
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desc->handle_irq = handle;
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#endif
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}
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static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
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extern void bfin_gpio_irq_prepare(unsigned gpio);
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#if !defined(CONFIG_BF54x)
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static void bfin_gpio_ack_irq(unsigned int irq)
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{
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/* AFAIK ack_irq in case mask_ack is provided
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* get's only called for edge sense irqs
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*/
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set_gpio_data(irq_to_gpio(irq), 0);
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}
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static void bfin_gpio_mask_ack_irq(unsigned int irq)
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{
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struct irq_desc *desc = irq_desc + irq;
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u32 gpionr = irq_to_gpio(irq);
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if (desc->handle_irq == handle_edge_irq)
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set_gpio_data(gpionr, 0);
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set_gpio_maska(gpionr, 0);
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}
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static void bfin_gpio_mask_irq(unsigned int irq)
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{
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set_gpio_maska(irq_to_gpio(irq), 0);
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}
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static void bfin_gpio_unmask_irq(unsigned int irq)
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{
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set_gpio_maska(irq_to_gpio(irq), 1);
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}
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static unsigned int bfin_gpio_irq_startup(unsigned int irq)
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{
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u32 gpionr = irq_to_gpio(irq);
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if (__test_and_set_bit(gpionr, gpio_enabled))
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bfin_gpio_irq_prepare(gpionr);
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bfin_gpio_unmask_irq(irq);
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return 0;
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}
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static void bfin_gpio_irq_shutdown(unsigned int irq)
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{
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u32 gpionr = irq_to_gpio(irq);
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bfin_gpio_mask_irq(irq);
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__clear_bit(gpionr, gpio_enabled);
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bfin_gpio_irq_free(gpionr);
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}
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static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
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{
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int ret;
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char buf[16];
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u32 gpionr = irq_to_gpio(irq);
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if (type == IRQ_TYPE_PROBE) {
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/* only probe unenabled GPIO interrupt lines */
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if (__test_bit(gpionr, gpio_enabled))
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return 0;
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type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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}
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
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IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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snprintf(buf, 16, "gpio-irq%d", irq);
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ret = bfin_gpio_irq_request(gpionr, buf);
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if (ret)
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return ret;
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if (__test_and_set_bit(gpionr, gpio_enabled))
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bfin_gpio_irq_prepare(gpionr);
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} else {
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__clear_bit(gpionr, gpio_enabled);
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return 0;
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}
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set_gpio_inen(gpionr, 0);
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set_gpio_dir(gpionr, 0);
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if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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== (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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set_gpio_both(gpionr, 1);
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else
|
|
set_gpio_both(gpionr, 0);
|
|
|
|
if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
|
|
set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
|
|
else
|
|
set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
|
|
|
|
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
|
|
set_gpio_edge(gpionr, 1);
|
|
set_gpio_inen(gpionr, 1);
|
|
set_gpio_data(gpionr, 0);
|
|
|
|
} else {
|
|
set_gpio_edge(gpionr, 0);
|
|
set_gpio_inen(gpionr, 1);
|
|
}
|
|
|
|
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
|
|
bfin_set_irq_handler(irq, handle_edge_irq);
|
|
else
|
|
bfin_set_irq_handler(irq, handle_level_irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
|
|
{
|
|
unsigned gpio = irq_to_gpio(irq);
|
|
|
|
if (state)
|
|
gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
|
|
else
|
|
gpio_pm_wakeup_free(gpio);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static void bfin_demux_gpio_irq(unsigned int inta_irq,
|
|
struct irq_desc *desc)
|
|
{
|
|
unsigned int i, gpio, mask, irq, search = 0;
|
|
|
|
switch (inta_irq) {
|
|
#if defined(CONFIG_BF53x)
|
|
case IRQ_PROG_INTA:
|
|
irq = IRQ_PF0;
|
|
search = 1;
|
|
break;
|
|
# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
|
|
case IRQ_MAC_RX:
|
|
irq = IRQ_PH0;
|
|
break;
|
|
# endif
|
|
#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
|
|
case IRQ_PORTF_INTA:
|
|
irq = IRQ_PF0;
|
|
break;
|
|
#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
|
|
case IRQ_PORTF_INTA:
|
|
irq = IRQ_PF0;
|
|
break;
|
|
case IRQ_PORTG_INTA:
|
|
irq = IRQ_PG0;
|
|
break;
|
|
case IRQ_PORTH_INTA:
|
|
irq = IRQ_PH0;
|
|
break;
|
|
#elif defined(CONFIG_BF561)
|
|
case IRQ_PROG0_INTA:
|
|
irq = IRQ_PF0;
|
|
break;
|
|
case IRQ_PROG1_INTA:
|
|
irq = IRQ_PF16;
|
|
break;
|
|
case IRQ_PROG2_INTA:
|
|
irq = IRQ_PF32;
|
|
break;
|
|
#endif
|
|
default:
|
|
BUG();
|
|
return;
|
|
}
|
|
|
|
if (search) {
|
|
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
|
|
irq += i;
|
|
|
|
mask = get_gpiop_data(i) & get_gpiop_maska(i);
|
|
|
|
while (mask) {
|
|
if (mask & 1)
|
|
bfin_handle_irq(irq);
|
|
irq++;
|
|
mask >>= 1;
|
|
}
|
|
}
|
|
} else {
|
|
gpio = irq_to_gpio(irq);
|
|
mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
|
|
|
|
do {
|
|
if (mask & 1)
|
|
bfin_handle_irq(irq);
|
|
irq++;
|
|
mask >>= 1;
|
|
} while (mask);
|
|
}
|
|
|
|
}
|
|
|
|
#else /* CONFIG_BF54x */
|
|
|
|
#define NR_PINT_SYS_IRQS 4
|
|
#define NR_PINT_BITS 32
|
|
#define NR_PINTS 160
|
|
#define IRQ_NOT_AVAIL 0xFF
|
|
|
|
#define PINT_2_BANK(x) ((x) >> 5)
|
|
#define PINT_2_BIT(x) ((x) & 0x1F)
|
|
#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
|
|
|
|
static unsigned char irq2pint_lut[NR_PINTS];
|
|
static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
|
|
|
|
struct pin_int_t {
|
|
unsigned int mask_set;
|
|
unsigned int mask_clear;
|
|
unsigned int request;
|
|
unsigned int assign;
|
|
unsigned int edge_set;
|
|
unsigned int edge_clear;
|
|
unsigned int invert_set;
|
|
unsigned int invert_clear;
|
|
unsigned int pinstate;
|
|
unsigned int latch;
|
|
};
|
|
|
|
static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
|
|
(struct pin_int_t *)PINT0_MASK_SET,
|
|
(struct pin_int_t *)PINT1_MASK_SET,
|
|
(struct pin_int_t *)PINT2_MASK_SET,
|
|
(struct pin_int_t *)PINT3_MASK_SET,
|
|
};
|
|
|
|
inline unsigned int get_irq_base(u32 bank, u8 bmap)
|
|
{
|
|
unsigned int irq_base;
|
|
|
|
if (bank < 2) { /*PA-PB */
|
|
irq_base = IRQ_PA0 + bmap * 16;
|
|
} else { /*PC-PJ */
|
|
irq_base = IRQ_PC0 + bmap * 16;
|
|
}
|
|
|
|
return irq_base;
|
|
}
|
|
|
|
/* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
|
|
void init_pint_lut(void)
|
|
{
|
|
u16 bank, bit, irq_base, bit_pos;
|
|
u32 pint_assign;
|
|
u8 bmap;
|
|
|
|
memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
|
|
|
|
for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
|
|
|
|
pint_assign = pint[bank]->assign;
|
|
|
|
for (bit = 0; bit < NR_PINT_BITS; bit++) {
|
|
|
|
bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
|
|
|
|
irq_base = get_irq_base(bank, bmap);
|
|
|
|
irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
|
|
bit_pos = bit + bank * NR_PINT_BITS;
|
|
|
|
pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
|
|
irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void bfin_gpio_ack_irq(unsigned int irq)
|
|
{
|
|
struct irq_desc *desc = irq_desc + irq;
|
|
u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
|
|
u32 pintbit = PINT_BIT(pint_val);
|
|
u32 bank = PINT_2_BANK(pint_val);
|
|
|
|
if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
|
|
if (pint[bank]->invert_set & pintbit)
|
|
pint[bank]->invert_clear = pintbit;
|
|
else
|
|
pint[bank]->invert_set = pintbit;
|
|
}
|
|
pint[bank]->request = pintbit;
|
|
|
|
}
|
|
|
|
static void bfin_gpio_mask_ack_irq(unsigned int irq)
|
|
{
|
|
struct irq_desc *desc = irq_desc + irq;
|
|
u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
|
|
u32 pintbit = PINT_BIT(pint_val);
|
|
u32 bank = PINT_2_BANK(pint_val);
|
|
|
|
if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
|
|
if (pint[bank]->invert_set & pintbit)
|
|
pint[bank]->invert_clear = pintbit;
|
|
else
|
|
pint[bank]->invert_set = pintbit;
|
|
}
|
|
|
|
pint[bank]->request = pintbit;
|
|
pint[bank]->mask_clear = pintbit;
|
|
}
|
|
|
|
static void bfin_gpio_mask_irq(unsigned int irq)
|
|
{
|
|
u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
|
|
|
|
pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
|
|
}
|
|
|
|
static void bfin_gpio_unmask_irq(unsigned int irq)
|
|
{
|
|
u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
|
|
u32 pintbit = PINT_BIT(pint_val);
|
|
u32 bank = PINT_2_BANK(pint_val);
|
|
|
|
pint[bank]->request = pintbit;
|
|
pint[bank]->mask_set = pintbit;
|
|
}
|
|
|
|
static unsigned int bfin_gpio_irq_startup(unsigned int irq)
|
|
{
|
|
u32 gpionr = irq_to_gpio(irq);
|
|
u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
|
|
|
|
if (pint_val == IRQ_NOT_AVAIL) {
|
|
printk(KERN_ERR
|
|
"GPIO IRQ %d :Not in PINT Assign table "
|
|
"Reconfigure Interrupt to Port Assignemt\n", irq);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (__test_and_set_bit(gpionr, gpio_enabled))
|
|
bfin_gpio_irq_prepare(gpionr);
|
|
|
|
bfin_gpio_unmask_irq(irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void bfin_gpio_irq_shutdown(unsigned int irq)
|
|
{
|
|
u32 gpionr = irq_to_gpio(irq);
|
|
|
|
bfin_gpio_mask_irq(irq);
|
|
__clear_bit(gpionr, gpio_enabled);
|
|
bfin_gpio_irq_free(gpionr);
|
|
}
|
|
|
|
static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
|
|
{
|
|
int ret;
|
|
char buf[16];
|
|
u32 gpionr = irq_to_gpio(irq);
|
|
u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
|
|
u32 pintbit = PINT_BIT(pint_val);
|
|
u32 bank = PINT_2_BANK(pint_val);
|
|
|
|
if (pint_val == IRQ_NOT_AVAIL)
|
|
return -ENODEV;
|
|
|
|
if (type == IRQ_TYPE_PROBE) {
|
|
/* only probe unenabled GPIO interrupt lines */
|
|
if (__test_bit(gpionr, gpio_enabled))
|
|
return 0;
|
|
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
|
|
}
|
|
|
|
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
|
|
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
|
|
|
|
snprintf(buf, 16, "gpio-irq%d", irq);
|
|
ret = bfin_gpio_irq_request(gpionr, buf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (__test_and_set_bit(gpionr, gpio_enabled))
|
|
bfin_gpio_irq_prepare(gpionr);
|
|
|
|
} else {
|
|
__clear_bit(gpionr, gpio_enabled);
|
|
return 0;
|
|
}
|
|
|
|
if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
|
|
pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
|
|
else
|
|
pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
|
|
|
|
if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
|
|
== (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
|
|
if (gpio_get_value(gpionr))
|
|
pint[bank]->invert_set = pintbit;
|
|
else
|
|
pint[bank]->invert_clear = pintbit;
|
|
}
|
|
|
|
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
|
|
pint[bank]->edge_set = pintbit;
|
|
bfin_set_irq_handler(irq, handle_edge_irq);
|
|
} else {
|
|
pint[bank]->edge_clear = pintbit;
|
|
bfin_set_irq_handler(irq, handle_level_irq);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
u32 pint_saved_masks[NR_PINT_SYS_IRQS];
|
|
u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
|
|
|
|
int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
|
|
{
|
|
u32 pint_irq;
|
|
u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
|
|
u32 bank = PINT_2_BANK(pint_val);
|
|
u32 pintbit = PINT_BIT(pint_val);
|
|
|
|
switch (bank) {
|
|
case 0:
|
|
pint_irq = IRQ_PINT0;
|
|
break;
|
|
case 2:
|
|
pint_irq = IRQ_PINT2;
|
|
break;
|
|
case 3:
|
|
pint_irq = IRQ_PINT3;
|
|
break;
|
|
case 1:
|
|
pint_irq = IRQ_PINT1;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
bfin_internal_set_wake(pint_irq, state);
|
|
|
|
if (state)
|
|
pint_wakeup_masks[bank] |= pintbit;
|
|
else
|
|
pint_wakeup_masks[bank] &= ~pintbit;
|
|
|
|
return 0;
|
|
}
|
|
|
|
u32 bfin_pm_setup(void)
|
|
{
|
|
u32 val, i;
|
|
|
|
for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
|
|
val = pint[i]->mask_clear;
|
|
pint_saved_masks[i] = val;
|
|
if (val ^ pint_wakeup_masks[i]) {
|
|
pint[i]->mask_clear = val;
|
|
pint[i]->mask_set = pint_wakeup_masks[i];
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void bfin_pm_restore(void)
|
|
{
|
|
u32 i, val;
|
|
|
|
for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
|
|
val = pint_saved_masks[i];
|
|
if (val ^ pint_wakeup_masks[i]) {
|
|
pint[i]->mask_clear = pint[i]->mask_clear;
|
|
pint[i]->mask_set = val;
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static void bfin_demux_gpio_irq(unsigned int inta_irq,
|
|
struct irq_desc *desc)
|
|
{
|
|
u32 bank, pint_val;
|
|
u32 request, irq;
|
|
|
|
switch (inta_irq) {
|
|
case IRQ_PINT0:
|
|
bank = 0;
|
|
break;
|
|
case IRQ_PINT2:
|
|
bank = 2;
|
|
break;
|
|
case IRQ_PINT3:
|
|
bank = 3;
|
|
break;
|
|
case IRQ_PINT1:
|
|
bank = 1;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
pint_val = bank * NR_PINT_BITS;
|
|
|
|
request = pint[bank]->request;
|
|
|
|
while (request) {
|
|
if (request & 1) {
|
|
irq = pint2irq_lut[pint_val] + SYS_IRQS;
|
|
bfin_handle_irq(irq);
|
|
}
|
|
pint_val++;
|
|
request >>= 1;
|
|
}
|
|
|
|
}
|
|
#endif
|
|
|
|
static struct irq_chip bfin_gpio_irqchip = {
|
|
.name = "GPIO",
|
|
.ack = bfin_gpio_ack_irq,
|
|
.mask = bfin_gpio_mask_irq,
|
|
.mask_ack = bfin_gpio_mask_ack_irq,
|
|
.unmask = bfin_gpio_unmask_irq,
|
|
.disable = bfin_gpio_mask_irq,
|
|
.enable = bfin_gpio_unmask_irq,
|
|
.set_type = bfin_gpio_irq_type,
|
|
.startup = bfin_gpio_irq_startup,
|
|
.shutdown = bfin_gpio_irq_shutdown,
|
|
#ifdef CONFIG_PM
|
|
.set_wake = bfin_gpio_set_wake,
|
|
#endif
|
|
};
|
|
|
|
void __cpuinit init_exception_vectors(void)
|
|
{
|
|
/* cannot program in software:
|
|
* evt0 - emulation (jtag)
|
|
* evt1 - reset
|
|
*/
|
|
bfin_write_EVT2(evt_nmi);
|
|
bfin_write_EVT3(trap);
|
|
bfin_write_EVT5(evt_ivhw);
|
|
bfin_write_EVT6(evt_timer);
|
|
bfin_write_EVT7(evt_evt7);
|
|
bfin_write_EVT8(evt_evt8);
|
|
bfin_write_EVT9(evt_evt9);
|
|
bfin_write_EVT10(evt_evt10);
|
|
bfin_write_EVT11(evt_evt11);
|
|
bfin_write_EVT12(evt_evt12);
|
|
bfin_write_EVT13(evt_evt13);
|
|
bfin_write_EVT14(evt14_softirq);
|
|
bfin_write_EVT15(evt_system_call);
|
|
CSYNC();
|
|
}
|
|
|
|
/*
|
|
* This function should be called during kernel startup to initialize
|
|
* the BFin IRQ handling routines.
|
|
*/
|
|
|
|
int __init init_arch_irq(void)
|
|
{
|
|
int irq;
|
|
unsigned long ilat = 0;
|
|
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
|
|
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
|
|
|| defined(BF538_FAMILY) || defined(CONFIG_BF51x)
|
|
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
|
|
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
|
|
# ifdef CONFIG_BF54x
|
|
bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
|
|
# endif
|
|
# ifdef CONFIG_SMP
|
|
bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
|
|
bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
|
|
# endif
|
|
#else
|
|
bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
|
|
#endif
|
|
|
|
local_irq_disable();
|
|
|
|
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
|
|
/* Clear EMAC Interrupt Status bits so we can demux it later */
|
|
bfin_write_EMAC_SYSTAT(-1);
|
|
#endif
|
|
|
|
#ifdef CONFIG_BF54x
|
|
# ifdef CONFIG_PINTx_REASSIGN
|
|
pint[0]->assign = CONFIG_PINT0_ASSIGN;
|
|
pint[1]->assign = CONFIG_PINT1_ASSIGN;
|
|
pint[2]->assign = CONFIG_PINT2_ASSIGN;
|
|
pint[3]->assign = CONFIG_PINT3_ASSIGN;
|
|
# endif
|
|
/* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
|
|
init_pint_lut();
|
|
#endif
|
|
|
|
for (irq = 0; irq <= SYS_IRQS; irq++) {
|
|
if (irq <= IRQ_CORETMR)
|
|
set_irq_chip(irq, &bfin_core_irqchip);
|
|
else
|
|
set_irq_chip(irq, &bfin_internal_irqchip);
|
|
|
|
switch (irq) {
|
|
#if defined(CONFIG_BF53x)
|
|
case IRQ_PROG_INTA:
|
|
# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
|
|
case IRQ_MAC_RX:
|
|
# endif
|
|
#elif defined(CONFIG_BF54x)
|
|
case IRQ_PINT0:
|
|
case IRQ_PINT1:
|
|
case IRQ_PINT2:
|
|
case IRQ_PINT3:
|
|
#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
|
|
case IRQ_PORTF_INTA:
|
|
case IRQ_PORTG_INTA:
|
|
case IRQ_PORTH_INTA:
|
|
#elif defined(CONFIG_BF561)
|
|
case IRQ_PROG0_INTA:
|
|
case IRQ_PROG1_INTA:
|
|
case IRQ_PROG2_INTA:
|
|
#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
|
|
case IRQ_PORTF_INTA:
|
|
#endif
|
|
|
|
set_irq_chained_handler(irq,
|
|
bfin_demux_gpio_irq);
|
|
break;
|
|
#ifdef BF537_GENERIC_ERROR_INT_DEMUX
|
|
case IRQ_GENERIC_ERROR:
|
|
set_irq_chained_handler(irq, bfin_demux_error_irq);
|
|
break;
|
|
#endif
|
|
#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
|
|
case IRQ_TIMER0:
|
|
set_irq_handler(irq, handle_percpu_irq);
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_SMP
|
|
case IRQ_SUPPLE_0:
|
|
case IRQ_SUPPLE_1:
|
|
set_irq_handler(irq, handle_percpu_irq);
|
|
break;
|
|
#endif
|
|
default:
|
|
#ifdef CONFIG_IPIPE
|
|
/*
|
|
* We want internal interrupt sources to be
|
|
* masked, because ISRs may trigger interrupts
|
|
* recursively (e.g. DMA), but interrupts are
|
|
* _not_ masked at CPU level. So let's handle
|
|
* most of them as level interrupts, except
|
|
* the timer interrupt which is special.
|
|
*/
|
|
if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR)
|
|
set_irq_handler(irq, handle_simple_irq);
|
|
else
|
|
set_irq_handler(irq, handle_level_irq);
|
|
#else /* !CONFIG_IPIPE */
|
|
set_irq_handler(irq, handle_simple_irq);
|
|
#endif /* !CONFIG_IPIPE */
|
|
break;
|
|
}
|
|
}
|
|
|
|
#ifdef BF537_GENERIC_ERROR_INT_DEMUX
|
|
for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
|
|
set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
|
|
handle_level_irq);
|
|
#endif
|
|
|
|
/* if configured as edge, then will be changed to do_edge_IRQ */
|
|
for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
|
|
set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
|
|
handle_level_irq);
|
|
|
|
|
|
bfin_write_IMASK(0);
|
|
CSYNC();
|
|
ilat = bfin_read_ILAT();
|
|
CSYNC();
|
|
bfin_write_ILAT(ilat);
|
|
CSYNC();
|
|
|
|
printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
|
|
/* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
|
|
* local_irq_enable()
|
|
*/
|
|
program_IAR();
|
|
/* Therefore it's better to setup IARs before interrupts enabled */
|
|
search_IAR();
|
|
|
|
/* Enable interrupts IVG7-15 */
|
|
bfin_irq_flags |= IMASK_IVG15 |
|
|
IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
|
|
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
|
|
|
|
#ifdef SIC_IWR0
|
|
bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
|
|
# ifdef SIC_IWR1
|
|
/* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
|
|
* will screw up the bootrom as it relies on MDMA0/1 waking it
|
|
* up from IDLE instructions. See this report for more info:
|
|
* http://blackfin.uclinux.org/gf/tracker/4323
|
|
*/
|
|
if (ANOMALY_05000435)
|
|
bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
|
|
else
|
|
bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
|
|
# endif
|
|
# ifdef SIC_IWR2
|
|
bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
|
|
# endif
|
|
#else
|
|
bfin_write_SIC_IWR(IWR_DISABLE_ALL);
|
|
#endif
|
|
|
|
#ifdef CONFIG_IPIPE
|
|
for (irq = 0; irq < NR_IRQS; irq++) {
|
|
struct irq_desc *desc = irq_to_desc(irq);
|
|
desc->ic_prio = __ipipe_get_irq_priority(irq);
|
|
}
|
|
#endif /* CONFIG_IPIPE */
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_DO_IRQ_L1
|
|
__attribute__((l1_text))
|
|
#endif
|
|
void do_irq(int vec, struct pt_regs *fp)
|
|
{
|
|
if (vec == EVT_IVTMR_P) {
|
|
vec = IRQ_CORETMR;
|
|
} else {
|
|
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
|
|
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
|
|
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
|
|
|| defined(BF538_FAMILY) || defined(CONFIG_BF51x)
|
|
unsigned long sic_status[3];
|
|
|
|
if (smp_processor_id()) {
|
|
#ifdef CONFIG_SMP
|
|
/* This will be optimized out in UP mode. */
|
|
sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
|
|
sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
|
|
#endif
|
|
} else {
|
|
sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
|
|
sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
|
|
}
|
|
#ifdef CONFIG_BF54x
|
|
sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
|
|
#endif
|
|
for (;; ivg++) {
|
|
if (ivg >= ivg_stop) {
|
|
atomic_inc(&num_spurious);
|
|
return;
|
|
}
|
|
if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
|
|
break;
|
|
}
|
|
#else
|
|
unsigned long sic_status;
|
|
|
|
sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
|
|
|
|
for (;; ivg++) {
|
|
if (ivg >= ivg_stop) {
|
|
atomic_inc(&num_spurious);
|
|
return;
|
|
} else if (sic_status & ivg->isrflag)
|
|
break;
|
|
}
|
|
#endif
|
|
vec = ivg->irqno;
|
|
}
|
|
asm_do_IRQ(vec, fp);
|
|
}
|
|
|
|
#ifdef CONFIG_IPIPE
|
|
|
|
int __ipipe_get_irq_priority(unsigned irq)
|
|
{
|
|
int ient, prio;
|
|
|
|
if (irq <= IRQ_CORETMR)
|
|
return irq;
|
|
|
|
for (ient = 0; ient < NR_PERI_INTS; ient++) {
|
|
struct ivgx *ivg = ivg_table + ient;
|
|
if (ivg->irqno == irq) {
|
|
for (prio = 0; prio <= IVG13-IVG7; prio++) {
|
|
if (ivg7_13[prio].ifirst <= ivg &&
|
|
ivg7_13[prio].istop > ivg)
|
|
return IVG7 + prio;
|
|
}
|
|
}
|
|
}
|
|
|
|
return IVG15;
|
|
}
|
|
|
|
/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
|
|
#ifdef CONFIG_DO_IRQ_L1
|
|
__attribute__((l1_text))
|
|
#endif
|
|
asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
|
|
{
|
|
struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
|
|
struct ipipe_domain *this_domain = ipipe_current_domain;
|
|
struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
|
|
struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
|
|
int irq, s;
|
|
|
|
if (likely(vec == EVT_IVTMR_P)) {
|
|
irq = IRQ_CORETMR;
|
|
goto core_tick;
|
|
}
|
|
|
|
SSYNC();
|
|
|
|
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
|
|
{
|
|
unsigned long sic_status[3];
|
|
|
|
sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
|
|
sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
|
|
#ifdef CONFIG_BF54x
|
|
sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
|
|
#endif
|
|
for (;; ivg++) {
|
|
if (ivg >= ivg_stop) {
|
|
atomic_inc(&num_spurious);
|
|
return 0;
|
|
}
|
|
if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
|
|
break;
|
|
}
|
|
}
|
|
#else
|
|
{
|
|
unsigned long sic_status;
|
|
|
|
sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
|
|
|
|
for (;; ivg++) {
|
|
if (ivg >= ivg_stop) {
|
|
atomic_inc(&num_spurious);
|
|
return 0;
|
|
} else if (sic_status & ivg->isrflag)
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
irq = ivg->irqno;
|
|
|
|
if (irq == IRQ_SYSTMR) {
|
|
#ifdef CONFIG_GENERIC_CLOCKEVENTS
|
|
core_tick:
|
|
#else
|
|
bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
|
|
#endif
|
|
/* This is basically what we need from the register frame. */
|
|
__raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
|
|
__raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
|
|
if (this_domain != ipipe_root_domain)
|
|
__raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
|
|
else
|
|
__raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
|
|
}
|
|
|
|
#ifndef CONFIG_GENERIC_CLOCKEVENTS
|
|
core_tick:
|
|
#endif
|
|
if (this_domain == ipipe_root_domain) {
|
|
s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
|
|
barrier();
|
|
}
|
|
|
|
ipipe_trace_irq_entry(irq);
|
|
__ipipe_handle_irq(irq, regs);
|
|
ipipe_trace_irq_exit(irq);
|
|
|
|
if (this_domain == ipipe_root_domain) {
|
|
set_thread_flag(TIF_IRQ_SYNC);
|
|
if (!s) {
|
|
__clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
|
|
return !test_bit(IPIPE_STALL_FLAG, &p->status);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_IPIPE */
|