c7fe7d25ed
Space for flushing the GPU cache prior to completing the request is preallocated and so cannot fail - the GPU caches will always be flushed along with the completed request. This means we no longer have to track whether the GPU cache is dirty between batches like we had to with the outstanding_lazy_seqno. With the removal of the duplication in the per-backend entry points for emitting the obsolete lazy flush, we can then further unify the engine->emit_flush. v2: Expand a bit on the legacy of gpu_caches_dirty Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-18-git-send-email-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1470174640-18242-7-git-send-email-chris@chris-wilson.co.uk
106 lines
4.2 KiB
C
106 lines
4.2 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#include "intel_ringbuffer.h"
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#define GEN8_LR_CONTEXT_ALIGN 4096
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/* Execlists regs */
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#define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
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#define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
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#define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
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#define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
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#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
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#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
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#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
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#define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
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#define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
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#define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
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#define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
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/* The docs specify that the write pointer wraps around after 5h, "After status
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* is written out to the last available status QW at offset 5h, this pointer
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* wraps to 0."
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*
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* Therefore, one must infer than even though there are 3 bits available, 6 and
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* 7 appear to be * reserved.
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*/
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#define GEN8_CSB_ENTRIES 6
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#define GEN8_CSB_PTR_MASK 0x7
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#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
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#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
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#define GEN8_CSB_WRITE_PTR(csb_status) \
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(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
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#define GEN8_CSB_READ_PTR(csb_status) \
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(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
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enum {
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INTEL_CONTEXT_SCHEDULE_IN = 0,
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INTEL_CONTEXT_SCHEDULE_OUT,
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};
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/* Logical Rings */
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int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
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int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
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void intel_logical_ring_stop(struct intel_engine_cs *engine);
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void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
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int logical_render_ring_init(struct intel_engine_cs *engine);
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int logical_xcs_ring_init(struct intel_engine_cs *engine);
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int intel_engines_init(struct drm_device *dev);
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/* Logical Ring Contexts */
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/* One extra page is added before LRC for GuC as shared data */
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#define LRC_GUCSHR_PN (0)
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#define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1)
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#define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
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struct i915_gem_context;
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uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
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void intel_lr_context_unpin(struct i915_gem_context *ctx,
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struct intel_engine_cs *engine);
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struct drm_i915_private;
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void intel_lr_context_reset(struct drm_i915_private *dev_priv,
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struct i915_gem_context *ctx);
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uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
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struct intel_engine_cs *engine);
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/* Execlists */
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int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
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int enable_execlists);
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struct i915_execbuffer_params;
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int intel_execlists_submission(struct i915_execbuffer_params *params,
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struct drm_i915_gem_execbuffer2 *args,
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struct list_head *vmas);
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void intel_execlists_cancel_requests(struct intel_engine_cs *engine);
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#endif /* _INTEL_LRC_H_ */
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