4f88bd23ba
This adds an interface for configuring Qualcomm's "secure SMMU" and adds support for booting the modem Hexagon on MSM8996. Two new debugfs entries are added in the remoteproc core to introspect the list of memory carveouts and the loaded resource table. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJaD26iAAoJEAsfOT8Nma3FUp0QAL/WZhL8QsvVFbAlv/Aa6NKm z8blXscD0GKdQWDWGaGPtpbnpOWOYhJs9WxstiB2q9ooSa9brIdjG5ukr4DTgtRs 12If5tfkVFIjlBhAdYYK+biNSQtZE+37jb7aJ+j4N3Po3O72pxekcLMLhAdvY6yk zHnhDZ8N7KBxAa0eOg7PJz7AGRF6BHhPxkqgJm0FzBj4HLQ/lwrv6iYJRrZgw6CT OhIHgPwCSHmt2fTO2QDLOWJtbVMSFhunHbuYlzPwvhMAGCT87VmXCIkW8iVhcD24 uJMrFbQoBoWVMB68JgGUKd7SSs8pV7DMrGfJll1kBEQfMLynn8Omre7WDAfwjUEn ACasSDWdWEPABJoIRVkGhS+2BnfCehdvDC7QxFFPAf8oc49O3t6DyXcCQdcVkzzE f1r/G2JKsoNQxjklFJewU5r0EjWgvV/78Dmpi7tuUtjgMSyEqkYORmInbbFIqZrU 9bHCqrmlxuRFSklxoG2u7F2SVYgMVlqM4rmj8QqR85SeIfyZtcCx5i5yAj8dZsI1 JVjucOCROHFqs/3SYFKlo6x4XHIchJD4p64QOXPCVhw7R1NXTPRTFBCQ75PKdiD1 d7kcGhdaz2cMeN1WRhIQ00lh/uiDNd4Ez7sDuU8MnWiEcIs1/ZP1LCHZTNttoljH rWZp4XlrhT+Vx91zV5u5 =lnNj -----END PGP SIGNATURE----- Merge tag 'rproc-v4.15' of git://github.com/andersson/remoteproc Pull remoteproc updates from Bjorn Andersson: "This adds an interface for configuring Qualcomm's "secure SMMU" and adds support for booting the modem Hexagon on MSM8996. Two new debugfs entries are added in the remoteproc core to introspect the list of memory carveouts and the loaded resource table" * tag 'rproc-v4.15' of git://github.com/andersson/remoteproc: remoteproc: qcom: Fix error handling paths in order to avoid memory leaks remoteproc: qcom: Drop pr_err in q6v5_xfer_mem_ownership() remoteproc: debug: add carveouts list dump feature remoteproc: debug: add resource table dump feature remoteproc: qcom: Add support for mss remoteproc on msm8996 remoteproc: qcom: Make secure world call for mem ownership switch remoteproc: qcom: refactor mss fw image loading sequence firmware: scm: Add new SCM call API for switching memory ownership
98 lines
4.1 KiB
C
98 lines
4.1 KiB
C
/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
|
|
* Copyright (C) 2015 Linaro Ltd.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 and
|
|
* only version 2 as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
#ifndef __QCOM_SCM_H
|
|
#define __QCOM_SCM_H
|
|
|
|
#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
|
|
#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
|
|
#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
|
|
#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
|
|
|
|
struct qcom_scm_hdcp_req {
|
|
u32 addr;
|
|
u32 val;
|
|
};
|
|
|
|
struct qcom_scm_vmperm {
|
|
int vmid;
|
|
int perm;
|
|
};
|
|
|
|
#define QCOM_SCM_VMID_HLOS 0x3
|
|
#define QCOM_SCM_VMID_MSS_MSA 0xF
|
|
#define QCOM_SCM_PERM_READ 0x4
|
|
#define QCOM_SCM_PERM_WRITE 0x2
|
|
#define QCOM_SCM_PERM_EXEC 0x1
|
|
#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
|
|
#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
|
|
|
|
#if IS_ENABLED(CONFIG_QCOM_SCM)
|
|
extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
|
extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
|
|
extern bool qcom_scm_is_available(void);
|
|
extern bool qcom_scm_hdcp_available(void);
|
|
extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
|
u32 *resp);
|
|
extern bool qcom_scm_pas_supported(u32 peripheral);
|
|
extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
|
|
size_t size);
|
|
extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
|
|
phys_addr_t size);
|
|
extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
|
|
extern int qcom_scm_pas_shutdown(u32 peripheral);
|
|
extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
|
|
unsigned int *src, struct qcom_scm_vmperm *newvm,
|
|
int dest_cnt);
|
|
extern void qcom_scm_cpu_power_down(u32 flags);
|
|
extern u32 qcom_scm_get_version(void);
|
|
extern int qcom_scm_set_remote_state(u32 state, u32 id);
|
|
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
|
|
extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
|
|
extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
|
|
extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
|
|
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
|
|
#else
|
|
static inline
|
|
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline
|
|
int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline bool qcom_scm_is_available(void) { return false; }
|
|
static inline bool qcom_scm_hdcp_available(void) { return false; }
|
|
static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
|
u32 *resp) { return -ENODEV; }
|
|
static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
|
|
static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
|
|
size_t size) { return -ENODEV; }
|
|
static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
|
|
phys_addr_t size) { return -ENODEV; }
|
|
static inline int
|
|
qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
|
|
static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
|
|
static inline void qcom_scm_cpu_power_down(u32 flags) {}
|
|
static inline u32 qcom_scm_get_version(void) { return 0; }
|
|
static inline u32
|
|
qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
|
|
static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
|
|
static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
|
|
static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
|
|
static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
|
|
static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
|
|
#endif
|
|
#endif
|