234 lines
6.5 KiB
C
234 lines
6.5 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <kvm/arm_vgic.h>
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#include <asm/kvm_mmu.h>
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#include <asm/kvm_asm.h>
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#include "vgic.h"
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void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
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u32 model = vcpu->kvm->arch.vgic.vgic_model;
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if (cpuif->vgic_misr & ICH_MISR_EOI) {
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unsigned long eisr_bmap = cpuif->vgic_eisr;
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int lr;
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for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
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u32 intid;
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u64 val = cpuif->vgic_lr[lr];
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if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
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intid = val & ICH_LR_VIRTUAL_ID_MASK;
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else
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intid = val & GICH_LR_VIRTUALID;
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WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
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kvm_notify_acked_irq(vcpu->kvm, 0,
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intid - VGIC_NR_PRIVATE_IRQS);
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}
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/*
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* In the next iterations of the vcpu loop, if we sync
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* the vgic state after flushing it, but before
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* entering the guest (this happens for pending
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* signals and vmid rollovers), then make sure we
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* don't pick up any old maintenance interrupts here.
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*/
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cpuif->vgic_eisr = 0;
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}
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cpuif->vgic_hcr &= ~ICH_HCR_UIE;
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}
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void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
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cpuif->vgic_hcr |= ICH_HCR_UIE;
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}
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void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
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u32 model = vcpu->kvm->arch.vgic.vgic_model;
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int lr;
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for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
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u64 val = cpuif->vgic_lr[lr];
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u32 intid;
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struct vgic_irq *irq;
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if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
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intid = val & ICH_LR_VIRTUAL_ID_MASK;
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else
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intid = val & GICH_LR_VIRTUALID;
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irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
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spin_lock(&irq->irq_lock);
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/* Always preserve the active bit */
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irq->active = !!(val & ICH_LR_ACTIVE_BIT);
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/* Edge is the only case where we preserve the pending bit */
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if (irq->config == VGIC_CONFIG_EDGE &&
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(val & ICH_LR_PENDING_BIT)) {
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irq->pending = true;
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if (vgic_irq_is_sgi(intid) &&
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model == KVM_DEV_TYPE_ARM_VGIC_V2) {
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u32 cpuid = val & GICH_LR_PHYSID_CPUID;
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cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
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irq->source |= (1 << cpuid);
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}
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}
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/* Clear soft pending state when level irqs have been acked */
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if (irq->config == VGIC_CONFIG_LEVEL &&
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!(val & ICH_LR_PENDING_BIT)) {
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irq->soft_pending = false;
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irq->pending = irq->line_level;
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}
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spin_unlock(&irq->irq_lock);
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}
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}
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/* Requires the irq to be locked already */
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void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
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{
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u32 model = vcpu->kvm->arch.vgic.vgic_model;
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u64 val = irq->intid;
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if (irq->pending) {
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val |= ICH_LR_PENDING_BIT;
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if (irq->config == VGIC_CONFIG_EDGE)
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irq->pending = false;
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if (vgic_irq_is_sgi(irq->intid) &&
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model == KVM_DEV_TYPE_ARM_VGIC_V2) {
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u32 src = ffs(irq->source);
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BUG_ON(!src);
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val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
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irq->source &= ~(1 << (src - 1));
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if (irq->source)
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irq->pending = true;
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}
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}
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if (irq->active)
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val |= ICH_LR_ACTIVE_BIT;
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if (irq->hw) {
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val |= ICH_LR_HW;
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val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
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} else {
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if (irq->config == VGIC_CONFIG_LEVEL)
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val |= ICH_LR_EOI;
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}
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/*
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* We currently only support Group1 interrupts, which is a
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* known defect. This needs to be addressed at some point.
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*/
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if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
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val |= ICH_LR_GROUP;
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val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
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vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
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}
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void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
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{
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vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
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}
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void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
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{
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u32 vmcr;
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vmcr = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
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vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
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vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
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vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
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vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
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}
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void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
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{
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u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
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vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
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vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
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vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
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vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
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}
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/**
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* vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
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* @node: pointer to the DT node
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*
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* Returns 0 if a GICv3 has been found, returns an error code otherwise
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*/
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int vgic_v3_probe(const struct gic_kvm_info *info)
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{
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u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
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/*
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* The ListRegs field is 5 bits, but there is a architectural
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* maximum of 16 list registers. Just ignore bit 4...
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*/
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kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
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kvm_vgic_global_state.can_emulate_gicv2 = false;
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if (!info->vcpu.start) {
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kvm_info("GICv3: no GICV resource entry\n");
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kvm_vgic_global_state.vcpu_base = 0;
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} else if (!PAGE_ALIGNED(info->vcpu.start)) {
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pr_warn("GICV physical address 0x%llx not page aligned\n",
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(unsigned long long)info->vcpu.start);
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kvm_vgic_global_state.vcpu_base = 0;
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} else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
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pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
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(unsigned long long)resource_size(&info->vcpu),
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PAGE_SIZE);
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kvm_vgic_global_state.vcpu_base = 0;
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} else {
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kvm_vgic_global_state.vcpu_base = info->vcpu.start;
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kvm_vgic_global_state.can_emulate_gicv2 = true;
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kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
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kvm_info("vgic-v2@%llx\n", info->vcpu.start);
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}
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if (kvm_vgic_global_state.vcpu_base == 0)
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kvm_info("disabling GICv2 emulation\n");
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kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
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kvm_vgic_global_state.vctrl_base = NULL;
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kvm_vgic_global_state.type = VGIC_V3;
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kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
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return 0;
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}
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