![Stephen Boyd](/assets/img/avatar_default.png)
The sched_clock.h include is under include/linux now. Cc: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
403 lines
9.2 KiB
C
403 lines
9.2 KiB
C
/*
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* linux/arch/arm/mach-clps711x/core.c
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*
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* Core support for the CLPS711x-based machines.
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*
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* Copyright (C) 2001,2011 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/sizes.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/clk-provider.h>
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#include <linux/sched_clock.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/system_misc.h>
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#include <mach/hardware.h>
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static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
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*clk_tint, *clk_spi;
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/*
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* This maps the generic CLPS711x registers
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*/
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static struct map_desc clps711x_io_desc[] __initdata = {
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{
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.virtual = (unsigned long)CLPS711X_VIRT_BASE,
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.pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
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.length = SZ_64K,
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.type = MT_DEVICE
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}
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};
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void __init clps711x_map_io(void)
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{
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iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
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}
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static void int1_mask(struct irq_data *d)
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{
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u32 intmr1;
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intmr1 = clps_readl(INTMR1);
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intmr1 &= ~(1 << d->irq);
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clps_writel(intmr1, INTMR1);
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}
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static void int1_eoi(struct irq_data *d)
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{
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switch (d->irq) {
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case IRQ_CSINT: clps_writel(0, COEOI); break;
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case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
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case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
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case IRQ_RTCMI: clps_writel(0, RTCEOI); break;
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case IRQ_TINT: clps_writel(0, TEOI); break;
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case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
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}
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}
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static void int1_unmask(struct irq_data *d)
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{
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u32 intmr1;
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intmr1 = clps_readl(INTMR1);
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intmr1 |= 1 << d->irq;
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clps_writel(intmr1, INTMR1);
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}
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static struct irq_chip int1_chip = {
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.name = "Interrupt Vector 1",
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.irq_eoi = int1_eoi,
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.irq_mask = int1_mask,
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.irq_unmask = int1_unmask,
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};
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static void int2_mask(struct irq_data *d)
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{
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u32 intmr2;
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intmr2 = clps_readl(INTMR2);
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intmr2 &= ~(1 << (d->irq - 16));
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clps_writel(intmr2, INTMR2);
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}
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static void int2_eoi(struct irq_data *d)
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{
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switch (d->irq) {
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case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
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}
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}
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static void int2_unmask(struct irq_data *d)
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{
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u32 intmr2;
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intmr2 = clps_readl(INTMR2);
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intmr2 |= 1 << (d->irq - 16);
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clps_writel(intmr2, INTMR2);
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}
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static struct irq_chip int2_chip = {
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.name = "Interrupt Vector 2",
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.irq_eoi = int2_eoi,
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.irq_mask = int2_mask,
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.irq_unmask = int2_unmask,
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};
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static void int3_mask(struct irq_data *d)
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{
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u32 intmr3;
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intmr3 = clps_readl(INTMR3);
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intmr3 &= ~(1 << (d->irq - 32));
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clps_writel(intmr3, INTMR3);
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}
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static void int3_unmask(struct irq_data *d)
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{
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u32 intmr3;
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intmr3 = clps_readl(INTMR3);
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intmr3 |= 1 << (d->irq - 32);
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clps_writel(intmr3, INTMR3);
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}
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static struct irq_chip int3_chip = {
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.name = "Interrupt Vector 3",
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.irq_mask = int3_mask,
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.irq_unmask = int3_unmask,
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};
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static struct {
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int nr;
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struct irq_chip *chip;
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irq_flow_handler_t handle;
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} clps711x_irqdescs[] __initdata = {
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{ IRQ_CSINT, &int1_chip, handle_fasteoi_irq, },
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{ IRQ_EINT1, &int1_chip, handle_level_irq, },
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{ IRQ_EINT2, &int1_chip, handle_level_irq, },
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{ IRQ_EINT3, &int1_chip, handle_level_irq, },
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{ IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, },
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{ IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, },
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{ IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, },
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{ IRQ_TINT, &int1_chip, handle_fasteoi_irq, },
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{ IRQ_UTXINT1, &int1_chip, handle_level_irq, },
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{ IRQ_URXINT1, &int1_chip, handle_level_irq, },
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{ IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, },
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{ IRQ_SSEOTI, &int1_chip, handle_level_irq, },
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{ IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, },
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{ IRQ_SS2RX, &int2_chip, handle_level_irq, },
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{ IRQ_SS2TX, &int2_chip, handle_level_irq, },
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{ IRQ_UTXINT2, &int2_chip, handle_level_irq, },
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{ IRQ_URXINT2, &int2_chip, handle_level_irq, },
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};
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void __init clps711x_init_irq(void)
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{
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unsigned int i;
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/* Disable interrupts */
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clps_writel(0, INTMR1);
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clps_writel(0, INTMR2);
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clps_writel(0, INTMR3);
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/* Clear down any pending interrupts */
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clps_writel(0, BLEOI);
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clps_writel(0, MCEOI);
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clps_writel(0, COEOI);
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clps_writel(0, TC1EOI);
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clps_writel(0, TC2EOI);
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clps_writel(0, RTCEOI);
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clps_writel(0, TEOI);
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clps_writel(0, UMSEOI);
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clps_writel(0, KBDEOI);
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clps_writel(0, SRXEOF);
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clps_writel(0xffffffff, DAISR);
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for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
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irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
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clps711x_irqdescs[i].chip,
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clps711x_irqdescs[i].handle);
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set_irq_flags(clps711x_irqdescs[i].nr,
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IRQF_VALID | IRQF_PROBE);
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}
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if (IS_ENABLED(CONFIG_FIQ)) {
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init_FIQ(0);
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irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip,
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handle_bad_irq);
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set_irq_flags(IRQ_DAIINT,
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IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
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}
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}
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static inline u32 fls16(u32 x)
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{
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u32 r = 15;
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if (!(x & 0xff00)) {
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x <<= 8;
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r -= 8;
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}
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if (!(x & 0xf000)) {
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x <<= 4;
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r -= 4;
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}
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if (!(x & 0xc000)) {
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x <<= 2;
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r -= 2;
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}
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if (!(x & 0x8000))
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r--;
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return r;
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}
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asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
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{
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do {
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u32 irqstat;
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void __iomem *base = CLPS711X_VIRT_BASE;
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irqstat = readw_relaxed(base + INTSR1) &
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readw_relaxed(base + INTMR1);
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if (irqstat)
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handle_IRQ(fls16(irqstat), regs);
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irqstat = readw_relaxed(base + INTSR2) &
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readw_relaxed(base + INTMR2);
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if (irqstat) {
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handle_IRQ(fls16(irqstat) + 16, regs);
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continue;
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}
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break;
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} while (1);
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}
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static u32 notrace clps711x_sched_clock_read(void)
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{
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return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
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}
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static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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disable_irq(IRQ_TC2OI);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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enable_irq(IRQ_TC2OI);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Not supported */
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_RESUME:
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/* Left event sources disabled, no more interrupts appear */
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break;
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}
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}
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static struct clock_event_device clockevent_clps711x = {
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.name = "clps711x-clockevent",
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.rating = 300,
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = clps711x_clockevent_set_mode,
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};
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static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
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{
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clockevent_clps711x.event_handler(&clockevent_clps711x);
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return IRQ_HANDLED;
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}
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static struct irqaction clps711x_timer_irq = {
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.name = "clps711x-timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = clps711x_timer_interrupt,
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};
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static void add_fixed_clk(struct clk *clk, const char *name, int rate)
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{
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clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
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clk_register_clkdev(clk, name, NULL);
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}
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void __init clps711x_timer_init(void)
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{
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int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
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u32 tmp;
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osc = 3686400;
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ext = 13000000;
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tmp = clps_readl(PLLR) >> 24;
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if (tmp)
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pll = (osc * tmp) / 2;
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else
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pll = 73728000; /* Default value */
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tmp = clps_readl(SYSFLG2);
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if (tmp & SYSFLG2_CKMODE) {
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cpu = ext;
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bus = cpu;
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spi = 135400;
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pll = 0;
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} else {
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cpu = pll;
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if (cpu >= 36864000)
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bus = cpu / 2;
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else
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bus = 36864000 / 2;
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spi = cpu / 576;
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}
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uart = bus / 10;
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if (tmp & SYSFLG2_CKMODE) {
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tmp = clps_readl(SYSCON2);
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if (tmp & SYSCON2_OSTB)
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timh = ext / 26;
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else
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timh = 541440;
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} else
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timh = DIV_ROUND_CLOSEST(cpu, 144);
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timl = DIV_ROUND_CLOSEST(timh, 256);
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/* All clocks are fixed */
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add_fixed_clk(clk_pll, "pll", pll);
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add_fixed_clk(clk_bus, "bus", bus);
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add_fixed_clk(clk_uart, "uart", uart);
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add_fixed_clk(clk_timerl, "timer_lf", timl);
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add_fixed_clk(clk_timerh, "timer_hf", timh);
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add_fixed_clk(clk_tint, "tint", 64);
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add_fixed_clk(clk_spi, "spi", spi);
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pr_info("CPU frequency set at %i Hz.\n", cpu);
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/* Start Timer1 in free running mode (Low frequency) */
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tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
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clps_writel(tmp, SYSCON1);
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setup_sched_clock(clps711x_sched_clock_read, 16, timl);
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clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
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"clps711x_clocksource", timl, 300, 16,
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clocksource_mmio_readw_down);
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/* Set Timer2 prescaler */
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clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
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/* Start Timer2 in prescale mode (High frequency)*/
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tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
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clps_writel(tmp, SYSCON1);
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clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
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setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
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}
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void clps711x_restart(enum reboot_mode mode, const char *cmd)
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{
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soft_restart(0);
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}
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static void clps711x_idle(void)
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{
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clps_writel(1, HALT);
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asm("mov r0, r0");
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asm("mov r0, r0");
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}
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void __init clps711x_init_early(void)
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{
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arm_pm_idle = clps711x_idle;
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}
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