![Linus Torvalds](/assets/img/avatar_default.png)
More multiplatform enablement for ARM platforms. The ones converted in this branch are: - bcm2835 - cns3xxx - sirf - nomadik - msx - spear - tegra - ux500 We're getting close to having most of them converted! One of the larger platforms remaining is Samsung Exynos, and there are a bunch of supporting patches in this merge window for it. There was a patch in this branch to a early version of multiplatform conversion, but it ended up being reverted due to need of more bake time. The revert commit is part of the branch since it would have required rebasing multiple dependent branches and they were stable by then. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRgg99AAoJEIwa5zzehBx3n78P/j0w/8v+F4dM29ba5M/tqbFI e3wpeFykZ/HJH+FFIEYfIablpfHsLB0LEMh0dZmwHESFC6eR0RfGL2jOkpfcH9Ne 7B/JIFN4l1iwqqKCXf+QbYL6e8YFxlJkg6BIB4KhNgliQoO/ASP/8EbcgROYuxmN KPVdw9laUCCvb5Ogh2NWVAkBHhVGAEiqK20r4TQz8alI8RUmMleWM3o+wLBWVhOO d3gtYSfuFSbrJfbpKSdycLizoV/NekdOC1A9Ov9YuOdw8DzNbrThCRQtu0tIUgxN JjfnGlEJLsJS9SESfr8SYWxTuhe/lB2dGqjQPvRtl2HGBhbtTlnWfQ0k2ZHdeJuD J50SLrGA2gN9E5PlHJXjYk8uhhGIq8bNTJ//CtDkfKTq1D7PuHVEpEctsaz3BBbM U+x9zP2v4FB+yrZu8w+gkQY/wDgHsxj08mT6BK0+l8ePdyQV22CvwmM5XlJFI03x 5J0nLYiYfef+ZN9rGgVrQbn+yv+IEkE4DmeiscjeVJE5LVdVrDpYGfx7UA7V0UA7 i3KRVpNKuy1v7GJDnKlEBPkmB+vgXTRXUPDVCuC4n0Hi5PYj4es1gY6AoXGF90wm vtKxGr/2XDLP7Ro+m0OXMttSgQShnmbrbOngfkWcFwUmG7cB3SSUUOGKM+2LNnXM MJTqVhPjkZ2GYBi/J6S/ =4hSo -----END PGP SIGNATURE----- Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC multiplatform updates from Olof Johansson: "More multiplatform enablement for ARM platforms. The ones converted in this branch are: - bcm2835 - cns3xxx - sirf - nomadik - msx - spear - tegra - ux500 We're getting close to having most of them converted! One of the larger platforms remaining is Samsung Exynos, and there are a bunch of supporting patches in this merge window for it. There was a patch in this branch to a early version of multiplatform conversion, but it ended up being reverted due to need of more bake time. The revert commit is part of the branch since it would have required rebasing multiple dependent branches and they were stable by then" * tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits) mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms clocksource: nomadik-mtu: fix up clocksource/timer Revert "ARM: exynos: enable multiplatform support" ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ" ARM: exynos: enable multiplatform support rtc: s3c: make header file local mtd: onenand/samsung: make regs-onenand.h file local thermal/exynos: remove unnecessary header inclusions mmc: sdhci-s3c: remove platform dependencies ARM: samsung: move mfc device definition to s5p-dev-mfc.c ARM: exynos: move debug-macro.S to include/debug/ ARM: exynos: prepare for sparse IRQ ARM: exynos: introduce EXYNOS_ATAGS symbol ARM: tegra: build assembly files with -march=armv7-a ARM: Push selects for TWD/SCU into machine entries ARM: ux500: build hotplug.o for ARMv7-a ARM: ux500: move to multiplatform ARM: ux500: make remaining headers local ARM: ux500: make irqs.h local to platform ARM: ux500: get rid of <mach/[hardware|db8500-regs].h> ...
378 lines
10 KiB
C
378 lines
10 KiB
C
/*
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* Copyright 1999 - 2003 ARM Limited
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* Copyright 2000 Deep Blue Solutions Ltd
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* Copyright 2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <linux/usb/ohci_pdriver.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "cns3xxx.h"
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#include "core.h"
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#include "pm.h"
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static struct map_desc cns3xxx_io_desc[] __initdata = {
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{
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.virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
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.length = SZ_8K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_MISC_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_PM_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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void __init cns3xxx_map_io(void)
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{
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iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
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}
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/* used by entry-macro.S */
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void __init cns3xxx_init_irq(void)
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{
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gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
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IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
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}
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void cns3xxx_power_off(void)
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{
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u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
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u32 clkctrl;
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printk(KERN_INFO "powering system down...\n");
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clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
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clkctrl &= 0xfffff1ff;
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clkctrl |= (0x5 << 9); /* Hibernate */
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writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
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}
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/*
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* Timer
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*/
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static void __iomem *cns3xxx_tmr1;
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static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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int pclk = cns3xxx_cpu_clock() / 8;
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int reload;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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reload = pclk * 20 / (3 * HZ) * 0x25000;
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writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set, and timer enabled in 'next_event' hook */
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ctrl |= (1 << 2) | (1 << 9);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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ctrl = 0;
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}
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writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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}
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static int cns3xxx_timer_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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return 0;
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}
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static struct clock_event_device cns3xxx_tmr1_clockevent = {
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.name = "cns3xxx timer1",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = cns3xxx_timer_set_mode,
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.set_next_event = cns3xxx_timer_set_next_event,
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.rating = 350,
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.cpumask = cpu_all_mask,
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};
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static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
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{
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cns3xxx_tmr1_clockevent.irq = timer_irq;
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clockevents_config_and_register(&cns3xxx_tmr1_clockevent,
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(cns3xxx_cpu_clock() >> 3) * 1000000,
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0xf, 0xffffffff);
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}
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
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u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
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u32 val;
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/* Clear the interrupt */
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val = readl(stat);
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writel(val & ~(1 << 2), stat);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction cns3xxx_timer_irq = {
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.name = "timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = cns3xxx_timer_interrupt,
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};
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/*
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* Set up the clock source and clock events devices
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*/
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static void __init __cns3xxx_timer_init(unsigned int timer_irq)
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{
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u32 val;
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u32 irq_mask;
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/*
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* Initialise to a known state (all timers off)
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*/
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/* disable timer1 and timer2 */
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writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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/* stop free running timer3 */
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writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
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/* timer1 */
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writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
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writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
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writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
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/* mask irq, non-mask timer1 overflow */
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irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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irq_mask &= ~(1 << 2);
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irq_mask |= 0x03;
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writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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/* down counter */
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val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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val |= (1 << 9);
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writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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/* timer2 */
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writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
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writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
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/* mask irq */
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irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
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writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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/* down counter */
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val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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val |= (1 << 10);
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writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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/* Make irqs happen for the system timer */
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setup_irq(timer_irq, &cns3xxx_timer_irq);
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cns3xxx_clockevents_init(timer_irq);
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}
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void __init cns3xxx_timer_init(void)
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{
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cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
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__cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
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}
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#ifdef CONFIG_CACHE_L2X0
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void __init cns3xxx_l2x0_init(void)
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{
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void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
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u32 val;
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if (WARN_ON(!base))
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return;
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/*
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* Tag RAM Control register
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*
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* bit[10:8] - 1 cycle of write accesses latency
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* bit[6:4] - 1 cycle of read accesses latency
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* bit[3:0] - 1 cycle of setup latency
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*
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* 1 cycle of latency for setup, read and write accesses
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*/
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val = readl(base + L2X0_TAG_LATENCY_CTRL);
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val &= 0xfffff888;
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writel(val, base + L2X0_TAG_LATENCY_CTRL);
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/*
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* Data RAM Control register
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*
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* bit[10:8] - 1 cycles of write accesses latency
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* bit[6:4] - 1 cycles of read accesses latency
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* bit[3:0] - 1 cycle of setup latency
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*
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* 1 cycle of latency for setup, read and write accesses
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*/
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val = readl(base + L2X0_DATA_LATENCY_CTRL);
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val &= 0xfffff888;
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writel(val, base + L2X0_DATA_LATENCY_CTRL);
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/* 32 KiB, 8-way, parity disable */
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l2x0_init(base, 0x00540000, 0xfe000fff);
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}
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#endif /* CONFIG_CACHE_L2X0 */
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static int csn3xxx_usb_power_on(struct platform_device *pdev)
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{
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/*
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* EHCI and OHCI share the same clock and power,
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* resetting twice would cause the 1st controller been reset.
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* Therefore only do power up at the first up device, and
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* power down at the last down device.
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*
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* Set USB AHB INCR length to 16
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*/
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if (atomic_inc_return(&usb_pwr_ref) == 1) {
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cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
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cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
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cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
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__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
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MISC_CHIP_CONFIG_REG);
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}
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return 0;
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}
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static void csn3xxx_usb_power_off(struct platform_device *pdev)
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{
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/*
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* EHCI and OHCI share the same clock and power,
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* resetting twice would cause the 1st controller been reset.
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* Therefore only do power up at the first up device, and
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* power down at the last down device.
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*/
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if (atomic_dec_return(&usb_pwr_ref) == 0)
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cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
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}
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static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
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.power_on = csn3xxx_usb_power_on,
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.power_off = csn3xxx_usb_power_off,
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};
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static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
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.num_ports = 1,
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.power_on = csn3xxx_usb_power_on,
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.power_off = csn3xxx_usb_power_off,
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};
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static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
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{ "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
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{ "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
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{ "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
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{ "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL },
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{},
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};
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static void __init cns3xxx_init(void)
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{
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struct device_node *dn;
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cns3xxx_l2x0_init();
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dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
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if (of_device_is_available(dn)) {
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u32 tmp;
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tmp = __raw_readl(MISC_SATA_POWER_MODE);
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tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
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tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
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__raw_writel(tmp, MISC_SATA_POWER_MODE);
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/* Enable SATA PHY */
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cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
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cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
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/* Enable SATA Clock */
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cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
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/* De-Asscer SATA Reset */
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cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
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}
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dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
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if (of_device_is_available(dn)) {
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u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
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u32 gpioa_pins = __raw_readl(gpioa);
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/* MMC/SD pins share with GPIOA */
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gpioa_pins |= 0x1fff0004;
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__raw_writel(gpioa_pins, gpioa);
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cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
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cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
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}
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pm_power_off = cns3xxx_power_off;
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of_platform_populate(NULL, of_default_bus_match_table,
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cns3xxx_auxdata, NULL);
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}
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static const char *cns3xxx_dt_compat[] __initdata = {
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"cavium,cns3410",
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"cavium,cns3420",
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NULL,
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};
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DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
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.dt_compat = cns3xxx_dt_compat,
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.nr_irqs = NR_IRQS_CNS3XXX,
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.map_io = cns3xxx_map_io,
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.init_irq = cns3xxx_init_irq,
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.init_time = cns3xxx_timer_init,
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.init_machine = cns3xxx_init,
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.restart = cns3xxx_restart,
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MACHINE_END
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