![Linus Walleij](/assets/img/avatar_default.png)
This augments the core machine code for the Integrator platforms to get their references to the core module device nodes by using compatible strings instead of predefined node names and rename the CP syscon node to be simply "syscon". Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
570 lines
14 KiB
C
570 lines
14 KiB
C
/*
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* linux/arch/arm/mach-integrator/integrator_ap.c
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*
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* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/syscore_ops.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/kmi.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/mtd/physmap.h>
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#include <linux/clk.h>
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#include <linux/platform_data/clk-integrator.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/stat.h>
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#include <linux/sys_soc.h>
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#include <linux/termios.h>
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#include <linux/sched_clock.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/setup.h>
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#include <asm/param.h> /* HZ */
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#include <asm/mach-types.h>
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#include <mach/lm.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "cm.h"
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#include "common.h"
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#include "pci_v3.h"
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/* Base address to the AP system controller */
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void __iomem *ap_syscon_base;
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/*
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* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
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* is the (PA >> 12).
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*
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* Setup a VA for the Integrator interrupt controller (for header #0,
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* just for now).
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*/
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#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
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#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
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#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
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/*
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* Logical Physical
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* ef000000 Cache flush
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* f1000000 10000000 Core module registers
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* f1100000 11000000 System controller registers
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* f1200000 12000000 EBI registers
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* f1300000 13000000 Counter/Timer
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* f1400000 14000000 Interrupt controller
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* f1600000 16000000 UART 0
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* f1700000 17000000 UART 1
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* f1a00000 1a000000 Debug LEDs
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* f1b00000 1b000000 GPIO
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*/
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static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}
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};
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static void __init ap_map_io(void)
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{
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iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
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pci_v3_early_init();
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}
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#ifdef CONFIG_PM
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static unsigned long ic_irq_enable;
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static int irq_suspend(void)
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{
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ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
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return 0;
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}
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static void irq_resume(void)
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{
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/* disable all irq sources */
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cm_clear_irqs();
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
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}
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#else
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#define irq_suspend NULL
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#define irq_resume NULL
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#endif
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static struct syscore_ops irq_syscore_ops = {
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.suspend = irq_suspend,
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.resume = irq_resume,
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};
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static int __init irq_syscore_init(void)
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{
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register_syscore_ops(&irq_syscore_ops);
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return 0;
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}
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device_initcall(irq_syscore_init);
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/*
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* Flash handling.
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*/
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#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
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#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
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static int ap_flash_init(struct platform_device *dev)
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{
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u32 tmp;
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
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ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
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tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
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writel(tmp, EBI_CSR1);
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if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
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writel(0xa05f, EBI_LOCK);
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writel(tmp, EBI_CSR1);
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writel(0, EBI_LOCK);
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}
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return 0;
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}
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static void ap_flash_exit(struct platform_device *dev)
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{
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u32 tmp;
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
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ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
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tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
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writel(tmp, EBI_CSR1);
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if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
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writel(0xa05f, EBI_LOCK);
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writel(tmp, EBI_CSR1);
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writel(0, EBI_LOCK);
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}
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}
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static void ap_flash_set_vpp(struct platform_device *pdev, int on)
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{
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if (on)
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
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ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
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else
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
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ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
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}
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static struct physmap_flash_data ap_flash_data = {
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.width = 4,
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.init = ap_flash_init,
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.exit = ap_flash_exit,
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.set_vpp = ap_flash_set_vpp,
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};
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/*
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* For the PL010 found in the Integrator/AP some of the UART control is
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* implemented in the system controller and accessed using a callback
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* from the driver.
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*/
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static void integrator_uart_set_mctrl(struct amba_device *dev,
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void __iomem *base, unsigned int mctrl)
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{
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unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
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u32 phybase = dev->res.start;
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if (phybase == INTEGRATOR_UART0_BASE) {
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/* UART0 */
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rts_mask = 1 << 4;
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dtr_mask = 1 << 5;
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} else {
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/* UART1 */
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rts_mask = 1 << 6;
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dtr_mask = 1 << 7;
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}
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if (mctrl & TIOCM_RTS)
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ctrlc |= rts_mask;
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else
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ctrls |= rts_mask;
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if (mctrl & TIOCM_DTR)
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ctrlc |= dtr_mask;
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else
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ctrls |= dtr_mask;
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__raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
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__raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
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}
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struct amba_pl010_data ap_uart_data = {
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.set_mctrl = integrator_uart_set_mctrl,
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};
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/*
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* Where is the timer (VA)?
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*/
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#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
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#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
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#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
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static unsigned long timer_reload;
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static u32 notrace integrator_read_sched_clock(void)
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{
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return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
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}
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static void integrator_clocksource_init(unsigned long inrate,
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void __iomem *base)
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{
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u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
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unsigned long rate = inrate;
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if (rate >= 1500000) {
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rate /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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writel(0xffff, base + TIMER_LOAD);
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writel(ctrl, base + TIMER_CTRL);
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clocksource_mmio_init(base + TIMER_VALUE, "timer2",
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rate, 200, 16, clocksource_mmio_readl_down);
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setup_sched_clock(integrator_read_sched_clock, 16, rate);
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}
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static void __iomem * clkevt_base;
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
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{
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u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
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/* Disable timer */
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writel(ctrl, clkevt_base + TIMER_CTRL);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* Enable the timer and start the periodic tick */
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writel(timer_reload, clkevt_base + TIMER_LOAD);
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ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Leave the timer disabled, .set_next_event will enable it */
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ctrl &= ~TIMER_CTRL_PERIODIC;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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default:
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/* Just leave in disabled state */
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break;
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}
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}
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static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
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{
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unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
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writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device integrator_clockevent = {
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.name = "timer1",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = clkevt_set_mode,
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.set_next_event = clkevt_set_next_event,
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.rating = 300,
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};
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static struct irqaction integrator_timer_irq = {
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.name = "timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = integrator_timer_interrupt,
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.dev_id = &integrator_clockevent,
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};
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static void integrator_clockevent_init(unsigned long inrate,
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void __iomem *base, int irq)
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{
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unsigned long rate = inrate;
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unsigned int ctrl = 0;
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clkevt_base = base;
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/* Calculate and program a divisor */
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if (rate > 0x100000 * HZ) {
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rate /= 256;
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ctrl |= TIMER_CTRL_DIV256;
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} else if (rate > 0x10000 * HZ) {
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rate /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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timer_reload = rate / HZ;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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setup_irq(irq, &integrator_timer_irq);
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clockevents_config_and_register(&integrator_clockevent,
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rate,
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1,
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0xffffU);
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}
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void __init ap_init_early(void)
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{
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}
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static void __init ap_of_timer_init(void)
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{
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struct device_node *node;
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const char *path;
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void __iomem *base;
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int err;
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int irq;
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struct clk *clk;
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unsigned long rate;
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clk = clk_get_sys("ap_timer", NULL);
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BUG_ON(IS_ERR(clk));
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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err = of_property_read_string(of_aliases,
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"arm,timer-primary", &path);
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if (WARN_ON(err))
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return;
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node = of_find_node_by_path(path);
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base = of_iomap(node, 0);
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if (WARN_ON(!base))
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return;
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writel(0, base + TIMER_CTRL);
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integrator_clocksource_init(rate, base);
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err = of_property_read_string(of_aliases,
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"arm,timer-secondary", &path);
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if (WARN_ON(err))
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return;
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node = of_find_node_by_path(path);
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base = of_iomap(node, 0);
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if (WARN_ON(!base))
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return;
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irq = irq_of_parse_and_map(node, 0);
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writel(0, base + TIMER_CTRL);
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integrator_clockevent_init(rate, base, irq);
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}
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static const struct of_device_id fpga_irq_of_match[] __initconst = {
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{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
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{ /* Sentinel */ }
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};
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static void __init ap_init_irq_of(void)
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{
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cm_init();
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of_irq_init(fpga_irq_of_match);
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integrator_clk_init(false);
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}
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/* For the Device Tree, add in the UART callbacks as AUXDATA */
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static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
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"rtc", NULL),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
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"uart0", &ap_uart_data),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
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"uart1", &ap_uart_data),
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OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
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"kmi0", NULL),
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OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
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"kmi1", NULL),
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OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
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"physmap-flash", &ap_flash_data),
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{ /* sentinel */ },
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};
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static const struct of_device_id ap_syscon_match[] = {
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{ .compatible = "arm,integrator-ap-syscon"},
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{ },
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};
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static void __init ap_init_of(void)
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{
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unsigned long sc_dec;
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struct device_node *root;
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struct device_node *syscon;
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struct device *parent;
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struct soc_device *soc_dev;
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struct soc_device_attribute *soc_dev_attr;
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u32 ap_sc_id;
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int err;
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int i;
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/* Here we create an SoC device for the root node */
|
|
root = of_find_node_by_path("/");
|
|
if (!root)
|
|
return;
|
|
|
|
syscon = of_find_matching_node(root, ap_syscon_match);
|
|
if (!syscon)
|
|
return;
|
|
|
|
ap_syscon_base = of_iomap(syscon, 0);
|
|
if (!ap_syscon_base)
|
|
return;
|
|
|
|
ap_sc_id = readl(ap_syscon_base);
|
|
|
|
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
|
|
if (!soc_dev_attr)
|
|
return;
|
|
|
|
err = of_property_read_string(root, "compatible",
|
|
&soc_dev_attr->soc_id);
|
|
if (err)
|
|
return;
|
|
err = of_property_read_string(root, "model", &soc_dev_attr->machine);
|
|
if (err)
|
|
return;
|
|
soc_dev_attr->family = "Integrator";
|
|
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
|
|
'A' + (ap_sc_id & 0x0f));
|
|
|
|
soc_dev = soc_device_register(soc_dev_attr);
|
|
if (IS_ERR(soc_dev)) {
|
|
kfree(soc_dev_attr->revision);
|
|
kfree(soc_dev_attr);
|
|
return;
|
|
}
|
|
|
|
parent = soc_device_to_device(soc_dev);
|
|
integrator_init_sysfs(parent, ap_sc_id);
|
|
|
|
of_platform_populate(root, of_default_bus_match_table,
|
|
ap_auxdata_lookup, parent);
|
|
|
|
sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
|
|
for (i = 0; i < 4; i++) {
|
|
struct lm_device *lmdev;
|
|
|
|
if ((sc_dec & (16 << i)) == 0)
|
|
continue;
|
|
|
|
lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
|
|
if (!lmdev)
|
|
continue;
|
|
|
|
lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
|
|
lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
|
|
lmdev->resource.flags = IORESOURCE_MEM;
|
|
lmdev->irq = irq_of_parse_and_map(syscon, i);
|
|
lmdev->id = i;
|
|
|
|
lm_device_register(lmdev);
|
|
}
|
|
}
|
|
|
|
static const char * ap_dt_board_compat[] = {
|
|
"arm,integrator-ap",
|
|
NULL,
|
|
};
|
|
|
|
DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
|
|
.reserve = integrator_reserve,
|
|
.map_io = ap_map_io,
|
|
.init_early = ap_init_early,
|
|
.init_irq = ap_init_irq_of,
|
|
.handle_irq = fpga_handle_irq,
|
|
.init_time = ap_of_timer_init,
|
|
.init_machine = ap_init_of,
|
|
.restart = integrator_restart,
|
|
.dt_compat = ap_dt_board_compat,
|
|
MACHINE_END
|