![Heiko Stuebner](/assets/img/avatar_default.png)
The s3c2412 dma init contained code to handle dma-direction specific settings. As now all s3c2412-dma-channels are direction-independent this is not needed anymore. As the s3c2412 also was the only user of this, it can go away completely. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
1466 lines
32 KiB
C
1466 lines
32 KiB
C
/*
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* Copyright 2003-2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 DMA core
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*
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifdef CONFIG_S3C2410_DMA_DEBUG
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#define DEBUG
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#endif
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/syscore_ops.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <mach/dma.h>
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#include <mach/map.h>
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#include <plat/dma-s3c24xx.h>
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#include <plat/regs-dma.h>
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/* io map for dma */
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static void __iomem *dma_base;
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static struct kmem_cache *dma_kmem;
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static int dma_channels;
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static struct s3c24xx_dma_selection dma_sel;
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/* debugging functions */
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#define BUF_MAGIC (0xcafebabe)
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#define dmawarn(fmt...) printk(KERN_DEBUG fmt)
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#define dma_regaddr(chan, reg) ((chan)->regs + (reg))
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#if 1
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#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
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#else
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static inline void
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dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
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{
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pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
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writel(val, dma_regaddr(chan, reg));
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}
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#endif
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#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
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/* captured register state for debug */
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struct s3c2410_dma_regstate {
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unsigned long dcsrc;
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unsigned long disrc;
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unsigned long dstat;
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unsigned long dcon;
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unsigned long dmsktrig;
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};
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#ifdef CONFIG_S3C2410_DMA_DEBUG
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/* dmadbg_showregs
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*
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* simple debug routine to print the current state of the dma registers
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*/
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static void
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dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
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{
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regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
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regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
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regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
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regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
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regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
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}
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static void
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dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
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struct s3c2410_dma_regstate *regs)
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{
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printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
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chan->number, fname, line,
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regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
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regs->dcon);
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}
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static void
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dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
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{
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struct s3c2410_dma_regstate state;
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dmadbg_capture(chan, &state);
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printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
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chan->number, fname, line, chan->load_state,
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chan->curr, chan->next, chan->end);
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dmadbg_dumpregs(fname, line, chan, &state);
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}
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static void
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dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
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{
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struct s3c2410_dma_regstate state;
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dmadbg_capture(chan, &state);
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dmadbg_dumpregs(fname, line, chan, &state);
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}
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#define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
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#define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
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#else
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#define dbg_showregs(chan) do { } while(0)
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#define dbg_showchan(chan) do { } while(0)
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#endif /* CONFIG_S3C2410_DMA_DEBUG */
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/* s3c2410_dma_stats_timeout
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*
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* Update DMA stats from timeout info
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*/
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static void
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s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
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{
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if (stats == NULL)
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return;
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if (val > stats->timeout_longest)
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stats->timeout_longest = val;
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if (val < stats->timeout_shortest)
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stats->timeout_shortest = val;
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stats->timeout_avg += val;
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}
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/* s3c2410_dma_waitforload
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*
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* wait for the DMA engine to load a buffer, and update the state accordingly
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*/
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static int
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s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
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{
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int timeout = chan->load_timeout;
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int took;
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if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
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printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
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return 0;
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}
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if (chan->stats != NULL)
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chan->stats->loads++;
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while (--timeout > 0) {
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if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
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took = chan->load_timeout - timeout;
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s3c2410_dma_stats_timeout(chan->stats, took);
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switch (chan->load_state) {
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case S3C2410_DMALOAD_1LOADED:
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chan->load_state = S3C2410_DMALOAD_1RUNNING;
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break;
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default:
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printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
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}
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return 1;
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}
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}
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if (chan->stats != NULL) {
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chan->stats->timeout_failed++;
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}
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return 0;
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}
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/* s3c2410_dma_loadbuffer
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*
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* load a buffer, and update the channel state
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*/
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static inline int
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s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
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struct s3c2410_dma_buf *buf)
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{
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unsigned long reload;
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if (buf == NULL) {
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dmawarn("buffer is NULL\n");
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return -EINVAL;
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}
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pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
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buf, (unsigned long)buf->data, buf->size);
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/* check the state of the channel before we do anything */
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if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
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dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
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}
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if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
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dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
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}
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/* it would seem sensible if we are the last buffer to not bother
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* with the auto-reload bit, so that the DMA engine will not try
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* and load another transfer after this one has finished...
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*/
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if (chan->load_state == S3C2410_DMALOAD_NONE) {
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pr_debug("load_state is none, checking for noreload (next=%p)\n",
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buf->next);
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reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
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} else {
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//pr_debug("load_state is %d => autoreload\n", chan->load_state);
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reload = S3C2410_DCON_AUTORELOAD;
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}
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if ((buf->data & 0xf0000000) != 0x30000000) {
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dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
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}
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writel(buf->data, chan->addr_reg);
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dma_wrreg(chan, S3C2410_DMA_DCON,
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chan->dcon | reload | (buf->size/chan->xfer_unit));
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chan->next = buf->next;
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/* update the state of the channel */
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switch (chan->load_state) {
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case S3C2410_DMALOAD_NONE:
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chan->load_state = S3C2410_DMALOAD_1LOADED;
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break;
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case S3C2410_DMALOAD_1RUNNING:
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chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
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break;
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default:
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dmawarn("dmaload: unknown state %d in loadbuffer\n",
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chan->load_state);
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break;
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}
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return 0;
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}
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/* s3c2410_dma_call_op
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*
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* small routine to call the op routine with the given op if it has been
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* registered
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*/
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static void
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s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
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{
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if (chan->op_fn != NULL) {
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(chan->op_fn)(chan, op);
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}
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}
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/* s3c2410_dma_buffdone
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*
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* small wrapper to check if callback routine needs to be called, and
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* if so, call it
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*/
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static inline void
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s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
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enum s3c2410_dma_buffresult result)
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{
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#if 0
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pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
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chan->callback_fn, buf, buf->id, buf->size, result);
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#endif
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if (chan->callback_fn != NULL) {
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(chan->callback_fn)(chan, buf->id, buf->size, result);
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}
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}
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/* s3c2410_dma_start
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*
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* start a dma channel going
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*/
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static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
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{
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unsigned long tmp;
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unsigned long flags;
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pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
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local_irq_save(flags);
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if (chan->state == S3C2410_DMA_RUNNING) {
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pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
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local_irq_restore(flags);
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return 0;
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}
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chan->state = S3C2410_DMA_RUNNING;
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/* check whether there is anything to load, and if not, see
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* if we can find anything to load
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*/
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if (chan->load_state == S3C2410_DMALOAD_NONE) {
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if (chan->next == NULL) {
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printk(KERN_ERR "dma%d: channel has nothing loaded\n",
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chan->number);
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chan->state = S3C2410_DMA_IDLE;
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local_irq_restore(flags);
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return -EINVAL;
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}
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s3c2410_dma_loadbuffer(chan, chan->next);
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}
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dbg_showchan(chan);
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/* enable the channel */
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if (!chan->irq_enabled) {
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enable_irq(chan->irq);
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chan->irq_enabled = 1;
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}
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/* start the channel going */
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tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
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tmp &= ~S3C2410_DMASKTRIG_STOP;
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tmp |= S3C2410_DMASKTRIG_ON;
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dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
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pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
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#if 0
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/* the dma buffer loads should take care of clearing the AUTO
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* reloading feature */
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tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
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tmp &= ~S3C2410_DCON_NORELOAD;
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dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
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#endif
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s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
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dbg_showchan(chan);
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/* if we've only loaded one buffer onto the channel, then chec
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* to see if we have another, and if so, try and load it so when
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* the first buffer is finished, the new one will be loaded onto
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* the channel */
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if (chan->next != NULL) {
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if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
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if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
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pr_debug("%s: buff not yet loaded, no more todo\n",
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__func__);
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} else {
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chan->load_state = S3C2410_DMALOAD_1RUNNING;
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s3c2410_dma_loadbuffer(chan, chan->next);
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}
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} else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
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s3c2410_dma_loadbuffer(chan, chan->next);
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}
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}
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local_irq_restore(flags);
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return 0;
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}
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/* s3c2410_dma_canload
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*
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* work out if we can queue another buffer into the DMA engine
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*/
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static int
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s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
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{
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if (chan->load_state == S3C2410_DMALOAD_NONE ||
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chan->load_state == S3C2410_DMALOAD_1RUNNING)
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return 1;
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return 0;
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}
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/* s3c2410_dma_enqueue
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*
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* queue an given buffer for dma transfer.
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*
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* id the device driver's id information for this buffer
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* data the physical address of the buffer data
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* size the size of the buffer in bytes
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*
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* If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
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* is checked, and if set, the channel is started. If this flag isn't set,
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* then an error will be returned.
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*
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* It is possible to queue more than one DMA buffer onto a channel at
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* once, and the code will deal with the re-loading of the next buffer
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* when necessary.
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*/
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int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
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dma_addr_t data, int size)
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{
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struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
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struct s3c2410_dma_buf *buf;
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unsigned long flags;
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if (chan == NULL)
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return -EINVAL;
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pr_debug("%s: id=%p, data=%08x, size=%d\n",
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__func__, id, (unsigned int)data, size);
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buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
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if (buf == NULL) {
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pr_debug("%s: out of memory (%ld alloc)\n",
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__func__, (long)sizeof(*buf));
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return -ENOMEM;
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}
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//pr_debug("%s: new buffer %p\n", __func__, buf);
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//dbg_showchan(chan);
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buf->next = NULL;
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buf->data = buf->ptr = data;
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buf->size = size;
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buf->id = id;
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buf->magic = BUF_MAGIC;
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local_irq_save(flags);
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if (chan->curr == NULL) {
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/* we've got nothing loaded... */
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pr_debug("%s: buffer %p queued onto empty channel\n",
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__func__, buf);
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chan->curr = buf;
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chan->end = buf;
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chan->next = NULL;
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} else {
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pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
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chan->number, __func__, buf);
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if (chan->end == NULL) {
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pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
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chan->number, __func__, chan);
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} else {
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chan->end->next = buf;
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chan->end = buf;
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}
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}
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/* if necessary, update the next buffer field */
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if (chan->next == NULL)
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chan->next = buf;
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/* check to see if we can load a buffer */
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if (chan->state == S3C2410_DMA_RUNNING) {
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if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
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if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
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printk(KERN_ERR "dma%d: loadbuffer:"
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"timeout loading buffer\n",
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chan->number);
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dbg_showchan(chan);
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local_irq_restore(flags);
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return -EINVAL;
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}
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}
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while (s3c2410_dma_canload(chan) && chan->next != NULL) {
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s3c2410_dma_loadbuffer(chan, chan->next);
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}
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} else if (chan->state == S3C2410_DMA_IDLE) {
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if (chan->flags & S3C2410_DMAF_AUTOSTART) {
|
|
s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
|
|
S3C2410_DMAOP_START);
|
|
}
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(s3c2410_dma_enqueue);
|
|
|
|
static inline void
|
|
s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
|
|
{
|
|
int magicok = (buf->magic == BUF_MAGIC);
|
|
|
|
buf->magic = -1;
|
|
|
|
if (magicok) {
|
|
kmem_cache_free(dma_kmem, buf);
|
|
} else {
|
|
printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
|
|
}
|
|
}
|
|
|
|
/* s3c2410_dma_lastxfer
|
|
*
|
|
* called when the system is out of buffers, to ensure that the channel
|
|
* is prepared for shutdown.
|
|
*/
|
|
|
|
static inline void
|
|
s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
|
|
{
|
|
#if 0
|
|
pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
|
|
chan->number, chan->load_state);
|
|
#endif
|
|
|
|
switch (chan->load_state) {
|
|
case S3C2410_DMALOAD_NONE:
|
|
break;
|
|
|
|
case S3C2410_DMALOAD_1LOADED:
|
|
if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
|
|
/* flag error? */
|
|
printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
|
|
chan->number, __func__);
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case S3C2410_DMALOAD_1LOADED_1RUNNING:
|
|
/* I believe in this case we do not have anything to do
|
|
* until the next buffer comes along, and we turn off the
|
|
* reload */
|
|
return;
|
|
|
|
default:
|
|
pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
|
|
chan->number, chan->load_state);
|
|
return;
|
|
|
|
}
|
|
|
|
/* hopefully this'll shut the damned thing up after the transfer... */
|
|
dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
|
|
}
|
|
|
|
|
|
#define dmadbg2(x...)
|
|
|
|
static irqreturn_t
|
|
s3c2410_dma_irq(int irq, void *devpw)
|
|
{
|
|
struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
|
|
struct s3c2410_dma_buf *buf;
|
|
|
|
buf = chan->curr;
|
|
|
|
dbg_showchan(chan);
|
|
|
|
/* modify the channel state */
|
|
|
|
switch (chan->load_state) {
|
|
case S3C2410_DMALOAD_1RUNNING:
|
|
/* TODO - if we are running only one buffer, we probably
|
|
* want to reload here, and then worry about the buffer
|
|
* callback */
|
|
|
|
chan->load_state = S3C2410_DMALOAD_NONE;
|
|
break;
|
|
|
|
case S3C2410_DMALOAD_1LOADED:
|
|
/* iirc, we should go back to NONE loaded here, we
|
|
* had a buffer, and it was never verified as being
|
|
* loaded.
|
|
*/
|
|
|
|
chan->load_state = S3C2410_DMALOAD_NONE;
|
|
break;
|
|
|
|
case S3C2410_DMALOAD_1LOADED_1RUNNING:
|
|
/* we'll worry about checking to see if another buffer is
|
|
* ready after we've called back the owner. This should
|
|
* ensure we do not wait around too long for the DMA
|
|
* engine to start the next transfer
|
|
*/
|
|
|
|
chan->load_state = S3C2410_DMALOAD_1LOADED;
|
|
break;
|
|
|
|
case S3C2410_DMALOAD_NONE:
|
|
printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
|
|
chan->number);
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
|
|
chan->number, chan->load_state);
|
|
break;
|
|
}
|
|
|
|
if (buf != NULL) {
|
|
/* update the chain to make sure that if we load any more
|
|
* buffers when we call the callback function, things should
|
|
* work properly */
|
|
|
|
chan->curr = buf->next;
|
|
buf->next = NULL;
|
|
|
|
if (buf->magic != BUF_MAGIC) {
|
|
printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
|
|
chan->number, __func__, buf);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
|
|
|
|
/* free resouces */
|
|
s3c2410_dma_freebuf(buf);
|
|
} else {
|
|
}
|
|
|
|
/* only reload if the channel is still running... our buffer done
|
|
* routine may have altered the state by requesting the dma channel
|
|
* to stop or shutdown... */
|
|
|
|
/* todo: check that when the channel is shut-down from inside this
|
|
* function, we cope with unsetting reload, etc */
|
|
|
|
if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
|
|
unsigned long flags;
|
|
|
|
switch (chan->load_state) {
|
|
case S3C2410_DMALOAD_1RUNNING:
|
|
/* don't need to do anything for this state */
|
|
break;
|
|
|
|
case S3C2410_DMALOAD_NONE:
|
|
/* can load buffer immediately */
|
|
break;
|
|
|
|
case S3C2410_DMALOAD_1LOADED:
|
|
if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
|
|
/* flag error? */
|
|
printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
|
|
chan->number, __func__);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
break;
|
|
|
|
case S3C2410_DMALOAD_1LOADED_1RUNNING:
|
|
goto no_load;
|
|
|
|
default:
|
|
printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
|
|
chan->number, chan->load_state);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
local_irq_save(flags);
|
|
s3c2410_dma_loadbuffer(chan, chan->next);
|
|
local_irq_restore(flags);
|
|
} else {
|
|
s3c2410_dma_lastxfer(chan);
|
|
|
|
/* see if we can stop this channel.. */
|
|
if (chan->load_state == S3C2410_DMALOAD_NONE) {
|
|
pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
|
|
chan->number, jiffies);
|
|
s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
|
|
S3C2410_DMAOP_STOP);
|
|
}
|
|
}
|
|
|
|
no_load:
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
|
|
|
|
/* s3c2410_request_dma
|
|
*
|
|
* get control of an dma channel
|
|
*/
|
|
|
|
int s3c2410_dma_request(enum dma_ch channel,
|
|
struct s3c2410_dma_client *client,
|
|
void *dev)
|
|
{
|
|
struct s3c2410_dma_chan *chan;
|
|
unsigned long flags;
|
|
int err;
|
|
|
|
pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
|
|
channel, client->name, dev);
|
|
|
|
local_irq_save(flags);
|
|
|
|
chan = s3c2410_dma_map_channel(channel);
|
|
if (chan == NULL) {
|
|
local_irq_restore(flags);
|
|
return -EBUSY;
|
|
}
|
|
|
|
dbg_showchan(chan);
|
|
|
|
chan->client = client;
|
|
chan->in_use = 1;
|
|
|
|
if (!chan->irq_claimed) {
|
|
pr_debug("dma%d: %s : requesting irq %d\n",
|
|
channel, __func__, chan->irq);
|
|
|
|
chan->irq_claimed = 1;
|
|
local_irq_restore(flags);
|
|
|
|
err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
|
|
client->name, (void *)chan);
|
|
|
|
local_irq_save(flags);
|
|
|
|
if (err) {
|
|
chan->in_use = 0;
|
|
chan->irq_claimed = 0;
|
|
local_irq_restore(flags);
|
|
|
|
printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
|
|
client->name, chan->irq, chan->number);
|
|
return err;
|
|
}
|
|
|
|
chan->irq_enabled = 1;
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
|
|
/* need to setup */
|
|
|
|
pr_debug("%s: channel initialised, %p\n", __func__, chan);
|
|
|
|
return chan->number | DMACH_LOW_LEVEL;
|
|
}
|
|
|
|
EXPORT_SYMBOL(s3c2410_dma_request);
|
|
|
|
/* s3c2410_dma_free
|
|
*
|
|
* release the given channel back to the system, will stop and flush
|
|
* any outstanding transfers, and ensure the channel is ready for the
|
|
* next claimant.
|
|
*
|
|
* Note, although a warning is currently printed if the freeing client
|
|
* info is not the same as the registrant's client info, the free is still
|
|
* allowed to go through.
|
|
*/
|
|
|
|
int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client)
|
|
{
|
|
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
|
unsigned long flags;
|
|
|
|
if (chan == NULL)
|
|
return -EINVAL;
|
|
|
|
local_irq_save(flags);
|
|
|
|
if (chan->client != client) {
|
|
printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
|
|
channel, chan->client, client);
|
|
}
|
|
|
|
/* sort out stopping and freeing the channel */
|
|
|
|
if (chan->state != S3C2410_DMA_IDLE) {
|
|
pr_debug("%s: need to stop dma channel %p\n",
|
|
__func__, chan);
|
|
|
|
/* possibly flush the channel */
|
|
s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
|
|
}
|
|
|
|
chan->client = NULL;
|
|
chan->in_use = 0;
|
|
|
|
if (chan->irq_claimed)
|
|
free_irq(chan->irq, (void *)chan);
|
|
|
|
chan->irq_claimed = 0;
|
|
|
|
if (!(channel & DMACH_LOW_LEVEL))
|
|
s3c_dma_chan_map[channel] = NULL;
|
|
|
|
local_irq_restore(flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(s3c2410_dma_free);
|
|
|
|
static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
|
|
{
|
|
unsigned long flags;
|
|
unsigned long tmp;
|
|
|
|
pr_debug("%s:\n", __func__);
|
|
|
|
dbg_showchan(chan);
|
|
|
|
local_irq_save(flags);
|
|
|
|
s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
|
|
|
|
tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
|
|
tmp |= S3C2410_DMASKTRIG_STOP;
|
|
//tmp &= ~S3C2410_DMASKTRIG_ON;
|
|
dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
|
|
|
|
#if 0
|
|
/* should also clear interrupts, according to WinCE BSP */
|
|
tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
|
|
tmp |= S3C2410_DCON_NORELOAD;
|
|
dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
|
|
#endif
|
|
|
|
/* should stop do this, or should we wait for flush? */
|
|
chan->state = S3C2410_DMA_IDLE;
|
|
chan->load_state = S3C2410_DMALOAD_NONE;
|
|
|
|
local_irq_restore(flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
|
|
{
|
|
unsigned long tmp;
|
|
unsigned int timeout = 0x10000;
|
|
|
|
while (timeout-- > 0) {
|
|
tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
|
|
|
|
if (!(tmp & S3C2410_DMASKTRIG_ON))
|
|
return;
|
|
}
|
|
|
|
pr_debug("dma%d: failed to stop?\n", chan->number);
|
|
}
|
|
|
|
|
|
/* s3c2410_dma_flush
|
|
*
|
|
* stop the channel, and remove all current and pending transfers
|
|
*/
|
|
|
|
static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
|
|
{
|
|
struct s3c2410_dma_buf *buf, *next;
|
|
unsigned long flags;
|
|
|
|
pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number);
|
|
|
|
dbg_showchan(chan);
|
|
|
|
local_irq_save(flags);
|
|
|
|
if (chan->state != S3C2410_DMA_IDLE) {
|
|
pr_debug("%s: stopping channel...\n", __func__ );
|
|
s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
|
|
}
|
|
|
|
buf = chan->curr;
|
|
if (buf == NULL)
|
|
buf = chan->next;
|
|
|
|
chan->curr = chan->next = chan->end = NULL;
|
|
|
|
if (buf != NULL) {
|
|
for ( ; buf != NULL; buf = next) {
|
|
next = buf->next;
|
|
|
|
pr_debug("%s: free buffer %p, next %p\n",
|
|
__func__, buf, buf->next);
|
|
|
|
s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
|
|
s3c2410_dma_freebuf(buf);
|
|
}
|
|
}
|
|
|
|
dbg_showregs(chan);
|
|
|
|
s3c2410_dma_waitforstop(chan);
|
|
|
|
#if 0
|
|
/* should also clear interrupts, according to WinCE BSP */
|
|
{
|
|
unsigned long tmp;
|
|
|
|
tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
|
|
tmp |= S3C2410_DCON_NORELOAD;
|
|
dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
|
|
}
|
|
#endif
|
|
|
|
dbg_showregs(chan);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
dbg_showchan(chan);
|
|
|
|
/* if we've only loaded one buffer onto the channel, then chec
|
|
* to see if we have another, and if so, try and load it so when
|
|
* the first buffer is finished, the new one will be loaded onto
|
|
* the channel */
|
|
|
|
if (chan->next != NULL) {
|
|
if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
|
|
|
|
if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
|
|
pr_debug("%s: buff not yet loaded, no more todo\n",
|
|
__func__);
|
|
} else {
|
|
chan->load_state = S3C2410_DMALOAD_1RUNNING;
|
|
s3c2410_dma_loadbuffer(chan, chan->next);
|
|
}
|
|
|
|
} else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
|
|
s3c2410_dma_loadbuffer(chan, chan->next);
|
|
}
|
|
}
|
|
|
|
|
|
local_irq_restore(flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
int
|
|
s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op)
|
|
{
|
|
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
|
|
|
if (chan == NULL)
|
|
return -EINVAL;
|
|
|
|
switch (op) {
|
|
case S3C2410_DMAOP_START:
|
|
return s3c2410_dma_start(chan);
|
|
|
|
case S3C2410_DMAOP_STOP:
|
|
return s3c2410_dma_dostop(chan);
|
|
|
|
case S3C2410_DMAOP_PAUSE:
|
|
case S3C2410_DMAOP_RESUME:
|
|
return -ENOENT;
|
|
|
|
case S3C2410_DMAOP_FLUSH:
|
|
return s3c2410_dma_flush(chan);
|
|
|
|
case S3C2410_DMAOP_STARTED:
|
|
return s3c2410_dma_started(chan);
|
|
|
|
case S3C2410_DMAOP_TIMEOUT:
|
|
return 0;
|
|
|
|
}
|
|
|
|
return -ENOENT; /* unknown, don't bother */
|
|
}
|
|
|
|
EXPORT_SYMBOL(s3c2410_dma_ctrl);
|
|
|
|
/* DMA configuration for each channel
|
|
*
|
|
* DISRCC -> source of the DMA (AHB,APB)
|
|
* DISRC -> source address of the DMA
|
|
* DIDSTC -> destination of the DMA (AHB,APD)
|
|
* DIDST -> destination address of the DMA
|
|
*/
|
|
|
|
/* s3c2410_dma_config
|
|
*
|
|
* xfersize: size of unit in bytes (1,2,4)
|
|
*/
|
|
|
|
int s3c2410_dma_config(enum dma_ch channel,
|
|
int xferunit)
|
|
{
|
|
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
|
unsigned int dcon;
|
|
|
|
pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__, channel, xferunit);
|
|
|
|
if (chan == NULL)
|
|
return -EINVAL;
|
|
|
|
dcon = chan->dcon & dma_sel.dcon_mask;
|
|
pr_debug("%s: dcon is %08x\n", __func__, dcon);
|
|
|
|
switch (chan->req_ch) {
|
|
case DMACH_I2S_IN:
|
|
case DMACH_I2S_OUT:
|
|
case DMACH_PCM_IN:
|
|
case DMACH_PCM_OUT:
|
|
case DMACH_MIC_IN:
|
|
default:
|
|
dcon |= S3C2410_DCON_HANDSHAKE;
|
|
dcon |= S3C2410_DCON_SYNC_PCLK;
|
|
break;
|
|
|
|
case DMACH_SDI:
|
|
/* note, ensure if need HANDSHAKE or not */
|
|
dcon |= S3C2410_DCON_SYNC_PCLK;
|
|
break;
|
|
|
|
case DMACH_XD0:
|
|
case DMACH_XD1:
|
|
dcon |= S3C2410_DCON_HANDSHAKE;
|
|
dcon |= S3C2410_DCON_SYNC_HCLK;
|
|
break;
|
|
}
|
|
|
|
switch (xferunit) {
|
|
case 1:
|
|
dcon |= S3C2410_DCON_BYTE;
|
|
break;
|
|
|
|
case 2:
|
|
dcon |= S3C2410_DCON_HALFWORD;
|
|
break;
|
|
|
|
case 4:
|
|
dcon |= S3C2410_DCON_WORD;
|
|
break;
|
|
|
|
default:
|
|
pr_debug("%s: bad transfer size %d\n", __func__, xferunit);
|
|
return -EINVAL;
|
|
}
|
|
|
|
dcon |= S3C2410_DCON_HWTRIG;
|
|
dcon |= S3C2410_DCON_INTREQ;
|
|
|
|
pr_debug("%s: dcon now %08x\n", __func__, dcon);
|
|
|
|
chan->dcon = dcon;
|
|
chan->xfer_unit = xferunit;
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(s3c2410_dma_config);
|
|
|
|
|
|
/* s3c2410_dma_devconfig
|
|
*
|
|
* configure the dma source/destination hardware type and address
|
|
*
|
|
* source: DMA_FROM_DEVICE: source is hardware
|
|
* DMA_TO_DEVICE: source is memory
|
|
*
|
|
* devaddr: physical address of the source
|
|
*/
|
|
|
|
int s3c2410_dma_devconfig(enum dma_ch channel,
|
|
enum dma_data_direction source,
|
|
unsigned long devaddr)
|
|
{
|
|
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
|
unsigned int hwcfg;
|
|
|
|
if (chan == NULL)
|
|
return -EINVAL;
|
|
|
|
pr_debug("%s: source=%d, devaddr=%08lx\n",
|
|
__func__, (int)source, devaddr);
|
|
|
|
chan->source = source;
|
|
chan->dev_addr = devaddr;
|
|
|
|
switch (chan->req_ch) {
|
|
case DMACH_XD0:
|
|
case DMACH_XD1:
|
|
hwcfg = 0; /* AHB */
|
|
break;
|
|
|
|
default:
|
|
hwcfg = S3C2410_DISRCC_APB;
|
|
}
|
|
|
|
/* always assume our peripheral desintation is a fixed
|
|
* address in memory. */
|
|
hwcfg |= S3C2410_DISRCC_INC;
|
|
|
|
switch (source) {
|
|
case DMA_FROM_DEVICE:
|
|
/* source is hardware */
|
|
pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
|
|
__func__, devaddr, hwcfg);
|
|
dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
|
|
dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
|
|
dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
|
|
|
|
chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
|
|
break;
|
|
|
|
case DMA_TO_DEVICE:
|
|
/* source is memory */
|
|
pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
|
|
__func__, devaddr, hwcfg);
|
|
dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
|
|
dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
|
|
dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
|
|
|
|
chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_ERR "dma%d: invalid source type (%d)\n",
|
|
channel, source);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(s3c2410_dma_devconfig);
|
|
|
|
/* s3c2410_dma_getposition
|
|
*
|
|
* returns the current transfer points for the dma source and destination
|
|
*/
|
|
|
|
int s3c2410_dma_getposition(enum dma_ch channel, dma_addr_t *src, dma_addr_t *dst)
|
|
{
|
|
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
|
|
|
if (chan == NULL)
|
|
return -EINVAL;
|
|
|
|
if (src != NULL)
|
|
*src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
|
|
|
|
if (dst != NULL)
|
|
*dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(s3c2410_dma_getposition);
|
|
|
|
/* system core operations */
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static void s3c2410_dma_suspend_chan(struct s3c2410_dma_chan *cp)
|
|
{
|
|
printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
|
|
|
|
if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
|
|
/* the dma channel is still working, which is probably
|
|
* a bad thing to do over suspend/resume. We stop the
|
|
* channel and assume that the client is either going to
|
|
* retry after resume, or that it is broken.
|
|
*/
|
|
|
|
printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
|
|
cp->number);
|
|
|
|
s3c2410_dma_dostop(cp);
|
|
}
|
|
}
|
|
|
|
static int s3c2410_dma_suspend(void)
|
|
{
|
|
struct s3c2410_dma_chan *cp = s3c2410_chans;
|
|
int channel;
|
|
|
|
for (channel = 0; channel < dma_channels; cp++, channel++)
|
|
s3c2410_dma_suspend_chan(cp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp)
|
|
{
|
|
unsigned int no = cp->number | DMACH_LOW_LEVEL;
|
|
|
|
/* restore channel's hardware configuration */
|
|
|
|
if (!cp->in_use)
|
|
return;
|
|
|
|
printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
|
|
|
|
s3c2410_dma_config(no, cp->xfer_unit);
|
|
s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
|
|
|
|
/* re-select the dma source for this channel */
|
|
|
|
if (cp->map != NULL)
|
|
dma_sel.select(cp, cp->map);
|
|
}
|
|
|
|
static void s3c2410_dma_resume(void)
|
|
{
|
|
struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1;
|
|
int channel;
|
|
|
|
for (channel = dma_channels - 1; channel >= 0; cp--, channel--)
|
|
s3c2410_dma_resume_chan(cp);
|
|
}
|
|
|
|
#else
|
|
#define s3c2410_dma_suspend NULL
|
|
#define s3c2410_dma_resume NULL
|
|
#endif /* CONFIG_PM */
|
|
|
|
struct syscore_ops dma_syscore_ops = {
|
|
.suspend = s3c2410_dma_suspend,
|
|
.resume = s3c2410_dma_resume,
|
|
};
|
|
|
|
/* kmem cache implementation */
|
|
|
|
static void s3c2410_dma_cache_ctor(void *p)
|
|
{
|
|
memset(p, 0, sizeof(struct s3c2410_dma_buf));
|
|
}
|
|
|
|
/* initialisation code */
|
|
|
|
static int __init s3c24xx_dma_syscore_init(void)
|
|
{
|
|
register_syscore_ops(&dma_syscore_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
late_initcall(s3c24xx_dma_syscore_init);
|
|
|
|
int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
|
|
unsigned int stride)
|
|
{
|
|
struct s3c2410_dma_chan *cp;
|
|
int channel;
|
|
int ret;
|
|
|
|
printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n");
|
|
|
|
dma_channels = channels;
|
|
|
|
dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
|
|
if (dma_base == NULL) {
|
|
printk(KERN_ERR "dma failed to remap register block\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dma_kmem = kmem_cache_create("dma_desc",
|
|
sizeof(struct s3c2410_dma_buf), 0,
|
|
SLAB_HWCACHE_ALIGN,
|
|
s3c2410_dma_cache_ctor);
|
|
|
|
if (dma_kmem == NULL) {
|
|
printk(KERN_ERR "dma failed to make kmem cache\n");
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
for (channel = 0; channel < channels; channel++) {
|
|
cp = &s3c2410_chans[channel];
|
|
|
|
memset(cp, 0, sizeof(struct s3c2410_dma_chan));
|
|
|
|
/* dma channel irqs are in order.. */
|
|
cp->number = channel;
|
|
cp->irq = channel + irq;
|
|
cp->regs = dma_base + (channel * stride);
|
|
|
|
/* point current stats somewhere */
|
|
cp->stats = &cp->stats_store;
|
|
cp->stats_store.timeout_shortest = LONG_MAX;
|
|
|
|
/* basic channel configuration */
|
|
|
|
cp->load_timeout = 1<<18;
|
|
|
|
printk("DMA channel %d at %p, irq %d\n",
|
|
cp->number, cp->regs, cp->irq);
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
kmem_cache_destroy(dma_kmem);
|
|
iounmap(dma_base);
|
|
dma_base = NULL;
|
|
return ret;
|
|
}
|
|
|
|
int __init s3c2410_dma_init(void)
|
|
{
|
|
return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
|
|
}
|
|
|
|
static inline int is_channel_valid(unsigned int channel)
|
|
{
|
|
return (channel & DMA_CH_VALID);
|
|
}
|
|
|
|
static struct s3c24xx_dma_order *dma_order;
|
|
|
|
|
|
/* s3c2410_dma_map_channel()
|
|
*
|
|
* turn the virtual channel number into a real, and un-used hardware
|
|
* channel.
|
|
*
|
|
* first, try the dma ordering given to us by either the relevant
|
|
* dma code, or the board. Then just find the first usable free
|
|
* channel
|
|
*/
|
|
|
|
static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
|
|
{
|
|
struct s3c24xx_dma_order_ch *ord = NULL;
|
|
struct s3c24xx_dma_map *ch_map;
|
|
struct s3c2410_dma_chan *dmach;
|
|
int ch;
|
|
|
|
if (dma_sel.map == NULL || channel > dma_sel.map_size)
|
|
return NULL;
|
|
|
|
ch_map = dma_sel.map + channel;
|
|
|
|
/* first, try the board mapping */
|
|
|
|
if (dma_order) {
|
|
ord = &dma_order->channels[channel];
|
|
|
|
for (ch = 0; ch < dma_channels; ch++) {
|
|
int tmp;
|
|
if (!is_channel_valid(ord->list[ch]))
|
|
continue;
|
|
|
|
tmp = ord->list[ch] & ~DMA_CH_VALID;
|
|
if (s3c2410_chans[tmp].in_use == 0) {
|
|
ch = tmp;
|
|
goto found;
|
|
}
|
|
}
|
|
|
|
if (ord->flags & DMA_CH_NEVER)
|
|
return NULL;
|
|
}
|
|
|
|
/* second, search the channel map for first free */
|
|
|
|
for (ch = 0; ch < dma_channels; ch++) {
|
|
if (!is_channel_valid(ch_map->channels[ch]))
|
|
continue;
|
|
|
|
if (s3c2410_chans[ch].in_use == 0) {
|
|
printk("mapped channel %d to %d\n", channel, ch);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (ch >= dma_channels)
|
|
return NULL;
|
|
|
|
/* update our channel mapping */
|
|
|
|
found:
|
|
dmach = &s3c2410_chans[ch];
|
|
dmach->map = ch_map;
|
|
dmach->req_ch = channel;
|
|
s3c_dma_chan_map[channel] = dmach;
|
|
|
|
/* select the channel */
|
|
|
|
(dma_sel.select)(dmach, ch_map);
|
|
|
|
return dmach;
|
|
}
|
|
|
|
static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
|
|
{
|
|
struct s3c24xx_dma_map *nmap;
|
|
size_t map_sz = sizeof(*nmap) * sel->map_size;
|
|
int ptr;
|
|
|
|
nmap = kmemdup(sel->map, map_sz, GFP_KERNEL);
|
|
if (nmap == NULL)
|
|
return -ENOMEM;
|
|
|
|
memcpy(&dma_sel, sel, sizeof(*sel));
|
|
|
|
dma_sel.map = nmap;
|
|
|
|
for (ptr = 0; ptr < sel->map_size; ptr++)
|
|
s3c24xx_dma_check_entry(nmap+ptr, ptr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
|
|
{
|
|
struct s3c24xx_dma_order *nord = dma_order;
|
|
|
|
if (nord == NULL)
|
|
nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
|
|
|
|
if (nord == NULL) {
|
|
printk(KERN_ERR "no memory to store dma channel order\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dma_order = nord;
|
|
memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
|
|
return 0;
|
|
}
|