![Tomasz Figa](/assets/img/avatar_default.png)
This patch allows bypassing most of legacy initialization when booting an S3C64xx-based board using device tree, by adding conditional checks for DT presence to initcalls which are no longer necessary when booting with DT.. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
763 lines
17 KiB
C
763 lines
17 KiB
C
/* linux/arch/arm/plat-s3c64xx/dma.c
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*
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* Copyright 2009 Openmoko, Inc.
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* Copyright 2009 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX DMA core
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* NOTE: Code in this file is not used when booting with Device Tree support.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/dmapool.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/amba/pl080.h>
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#include <linux/of.h>
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#include <mach/dma.h>
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#include <mach/map.h>
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#include <mach/irqs.h>
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#include "regs-sys.h"
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/* dma channel state information */
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struct s3c64xx_dmac {
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struct device dev;
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struct clk *clk;
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void __iomem *regs;
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struct s3c2410_dma_chan *channels;
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enum dma_ch chanbase;
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};
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/* pool to provide LLI buffers */
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static struct dma_pool *dma_pool;
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/* Debug configuration and code */
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static unsigned char debug_show_buffs = 0;
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static void dbg_showchan(struct s3c2410_dma_chan *chan)
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{
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pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n",
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chan->number,
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readl(chan->regs + PL080_CH_SRC_ADDR),
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readl(chan->regs + PL080_CH_DST_ADDR),
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readl(chan->regs + PL080_CH_LLI),
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readl(chan->regs + PL080_CH_CONTROL),
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readl(chan->regs + PL080S_CH_CONTROL2),
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readl(chan->regs + PL080S_CH_CONFIG));
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}
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static void show_lli(struct pl080s_lli *lli)
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{
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pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n",
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lli, lli->src_addr, lli->dst_addr, lli->next_lli,
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lli->control0, lli->control1);
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}
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static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
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{
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struct s3c64xx_dma_buff *ptr;
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struct s3c64xx_dma_buff *end;
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pr_debug("DMA%d: buffs next %p, curr %p, end %p\n",
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chan->number, chan->next, chan->curr, chan->end);
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ptr = chan->next;
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end = chan->end;
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if (debug_show_buffs) {
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for (; ptr != NULL; ptr = ptr->next) {
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pr_debug("DMA%d: %08x ",
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chan->number, ptr->lli_dma);
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show_lli(ptr->lli);
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}
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}
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}
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/* End of Debug */
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static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
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{
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struct s3c2410_dma_chan *chan;
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unsigned int start, offs;
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start = 0;
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if (channel >= DMACH_PCM1_TX)
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start = 8;
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for (offs = 0; offs < 8; offs++) {
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chan = &s3c2410_chans[start + offs];
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if (!chan->in_use)
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goto found;
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}
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return NULL;
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found:
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s3c_dma_chan_map[channel] = chan;
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return chan;
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}
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int s3c2410_dma_config(enum dma_ch channel, int xferunit)
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{
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struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
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if (chan == NULL)
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return -EINVAL;
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switch (xferunit) {
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case 1:
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chan->hw_width = 0;
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break;
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case 2:
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chan->hw_width = 1;
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break;
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case 4:
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chan->hw_width = 2;
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break;
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default:
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printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit);
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return -EINVAL;
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}
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return 0;
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}
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EXPORT_SYMBOL(s3c2410_dma_config);
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static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
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struct pl080s_lli *lli,
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dma_addr_t data, int size)
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{
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dma_addr_t src, dst;
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u32 control0, control1;
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switch (chan->source) {
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case DMA_FROM_DEVICE:
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src = chan->dev_addr;
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dst = data;
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control0 = PL080_CONTROL_SRC_AHB2;
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control0 |= PL080_CONTROL_DST_INCR;
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break;
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case DMA_TO_DEVICE:
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src = data;
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dst = chan->dev_addr;
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control0 = PL080_CONTROL_DST_AHB2;
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control0 |= PL080_CONTROL_SRC_INCR;
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break;
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default:
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BUG();
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}
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/* note, we do not currently setup any of the burst controls */
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control1 = size >> chan->hw_width; /* size in no of xfers */
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control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */
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control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */
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control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
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control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
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lli->src_addr = src;
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lli->dst_addr = dst;
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lli->next_lli = 0;
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lli->control0 = control0;
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lli->control1 = control1;
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}
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static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan,
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struct pl080s_lli *lli)
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{
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void __iomem *regs = chan->regs;
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pr_debug("%s: LLI %p => regs\n", __func__, lli);
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show_lli(lli);
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writel(lli->src_addr, regs + PL080_CH_SRC_ADDR);
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writel(lli->dst_addr, regs + PL080_CH_DST_ADDR);
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writel(lli->next_lli, regs + PL080_CH_LLI);
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writel(lli->control0, regs + PL080_CH_CONTROL);
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writel(lli->control1, regs + PL080S_CH_CONTROL2);
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}
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static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
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{
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struct s3c64xx_dmac *dmac = chan->dmac;
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u32 config;
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u32 bit = chan->bit;
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dbg_showchan(chan);
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pr_debug("%s: clearing interrupts\n", __func__);
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/* clear interrupts */
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writel(bit, dmac->regs + PL080_TC_CLEAR);
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writel(bit, dmac->regs + PL080_ERR_CLEAR);
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pr_debug("%s: starting channel\n", __func__);
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config = readl(chan->regs + PL080S_CH_CONFIG);
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config |= PL080_CONFIG_ENABLE;
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config &= ~PL080_CONFIG_HALT;
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pr_debug("%s: writing config %08x\n", __func__, config);
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writel(config, chan->regs + PL080S_CH_CONFIG);
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return 0;
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}
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static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan)
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{
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u32 config;
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int timeout;
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pr_debug("%s: stopping channel\n", __func__);
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dbg_showchan(chan);
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config = readl(chan->regs + PL080S_CH_CONFIG);
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config |= PL080_CONFIG_HALT;
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writel(config, chan->regs + PL080S_CH_CONFIG);
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timeout = 1000;
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do {
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config = readl(chan->regs + PL080S_CH_CONFIG);
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pr_debug("%s: %d - config %08x\n", __func__, timeout, config);
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if (config & PL080_CONFIG_ACTIVE)
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udelay(10);
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else
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break;
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} while (--timeout > 0);
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if (config & PL080_CONFIG_ACTIVE) {
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printk(KERN_ERR "%s: channel still active\n", __func__);
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return -EFAULT;
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}
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config = readl(chan->regs + PL080S_CH_CONFIG);
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config &= ~PL080_CONFIG_ENABLE;
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writel(config, chan->regs + PL080S_CH_CONFIG);
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return 0;
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}
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static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan,
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struct s3c64xx_dma_buff *buf,
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enum s3c2410_dma_buffresult result)
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{
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if (chan->callback_fn != NULL)
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(chan->callback_fn)(chan, buf->pw, 0, result);
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}
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static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff)
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{
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dma_pool_free(dma_pool, buff->lli, buff->lli_dma);
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kfree(buff);
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}
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static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
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{
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struct s3c64xx_dma_buff *buff, *next;
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u32 config;
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dbg_showchan(chan);
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pr_debug("%s: flushing channel\n", __func__);
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config = readl(chan->regs + PL080S_CH_CONFIG);
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config &= ~PL080_CONFIG_ENABLE;
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writel(config, chan->regs + PL080S_CH_CONFIG);
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/* dump all the buffers associated with this channel */
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for (buff = chan->curr; buff != NULL; buff = next) {
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next = buff->next;
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pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next);
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s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT);
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s3c64xx_dma_freebuff(buff);
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}
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chan->curr = chan->next = chan->end = NULL;
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return 0;
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}
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int s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op)
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{
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struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
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WARN_ON(!chan);
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if (!chan)
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return -EINVAL;
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switch (op) {
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case S3C2410_DMAOP_START:
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return s3c64xx_dma_start(chan);
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case S3C2410_DMAOP_STOP:
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return s3c64xx_dma_stop(chan);
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case S3C2410_DMAOP_FLUSH:
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return s3c64xx_dma_flush(chan);
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/* believe PAUSE/RESUME are no-ops */
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case S3C2410_DMAOP_PAUSE:
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case S3C2410_DMAOP_RESUME:
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case S3C2410_DMAOP_STARTED:
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case S3C2410_DMAOP_TIMEOUT:
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return 0;
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}
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return -ENOENT;
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}
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EXPORT_SYMBOL(s3c2410_dma_ctrl);
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/* s3c2410_dma_enque
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*
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*/
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int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
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dma_addr_t data, int size)
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{
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struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
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struct s3c64xx_dma_buff *next;
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struct s3c64xx_dma_buff *buff;
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struct pl080s_lli *lli;
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unsigned long flags;
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int ret;
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WARN_ON(!chan);
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if (!chan)
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return -EINVAL;
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buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_ATOMIC);
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if (!buff) {
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printk(KERN_ERR "%s: no memory for buffer\n", __func__);
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return -ENOMEM;
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}
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lli = dma_pool_alloc(dma_pool, GFP_ATOMIC, &buff->lli_dma);
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if (!lli) {
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printk(KERN_ERR "%s: no memory for lli\n", __func__);
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ret = -ENOMEM;
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goto err_buff;
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}
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pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n",
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__func__, buff, data, lli, (u32)buff->lli_dma, size);
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buff->lli = lli;
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buff->pw = id;
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s3c64xx_dma_fill_lli(chan, lli, data, size);
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local_irq_save(flags);
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if ((next = chan->next) != NULL) {
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struct s3c64xx_dma_buff *end = chan->end;
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struct pl080s_lli *endlli = end->lli;
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pr_debug("enquing onto channel\n");
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end->next = buff;
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endlli->next_lli = buff->lli_dma;
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if (chan->flags & S3C2410_DMAF_CIRCULAR) {
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struct s3c64xx_dma_buff *curr = chan->curr;
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lli->next_lli = curr->lli_dma;
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}
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if (next == chan->curr) {
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writel(buff->lli_dma, chan->regs + PL080_CH_LLI);
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chan->next = buff;
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}
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show_lli(endlli);
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chan->end = buff;
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} else {
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pr_debug("enquing onto empty channel\n");
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chan->curr = buff;
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chan->next = buff;
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chan->end = buff;
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s3c64xx_lli_to_regs(chan, lli);
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}
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local_irq_restore(flags);
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show_lli(lli);
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dbg_showchan(chan);
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dbg_showbuffs(chan);
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return 0;
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err_buff:
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kfree(buff);
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return ret;
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}
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EXPORT_SYMBOL(s3c2410_dma_enqueue);
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int s3c2410_dma_devconfig(enum dma_ch channel,
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enum dma_data_direction source,
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unsigned long devaddr)
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{
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struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
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u32 peripheral;
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u32 config = 0;
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pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n",
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__func__, channel, source, devaddr, chan);
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WARN_ON(!chan);
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if (!chan)
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return -EINVAL;
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peripheral = (chan->peripheral & 0xf);
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chan->source = source;
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chan->dev_addr = devaddr;
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pr_debug("%s: peripheral %d\n", __func__, peripheral);
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switch (source) {
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case DMA_FROM_DEVICE:
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config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
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break;
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case DMA_TO_DEVICE:
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config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
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break;
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default:
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printk(KERN_ERR "%s: bad source\n", __func__);
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return -EINVAL;
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}
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/* allow TC and ERR interrupts */
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config |= PL080_CONFIG_TC_IRQ_MASK;
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config |= PL080_CONFIG_ERR_IRQ_MASK;
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pr_debug("%s: config %08x\n", __func__, config);
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writel(config, chan->regs + PL080S_CH_CONFIG);
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return 0;
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}
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EXPORT_SYMBOL(s3c2410_dma_devconfig);
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int s3c2410_dma_getposition(enum dma_ch channel,
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dma_addr_t *src, dma_addr_t *dst)
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{
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struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
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WARN_ON(!chan);
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if (!chan)
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return -EINVAL;
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if (src != NULL)
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*src = readl(chan->regs + PL080_CH_SRC_ADDR);
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if (dst != NULL)
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*dst = readl(chan->regs + PL080_CH_DST_ADDR);
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return 0;
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}
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EXPORT_SYMBOL(s3c2410_dma_getposition);
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/* s3c2410_request_dma
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*
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* get control of an dma channel
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*/
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int s3c2410_dma_request(enum dma_ch channel,
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struct s3c2410_dma_client *client,
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void *dev)
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{
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struct s3c2410_dma_chan *chan;
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unsigned long flags;
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pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
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channel, client->name, dev);
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local_irq_save(flags);
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chan = s3c64xx_dma_map_channel(channel);
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if (chan == NULL) {
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local_irq_restore(flags);
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return -EBUSY;
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}
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dbg_showchan(chan);
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chan->client = client;
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chan->in_use = 1;
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chan->peripheral = channel;
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chan->flags = 0;
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local_irq_restore(flags);
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/* need to setup */
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pr_debug("%s: channel initialised, %p\n", __func__, chan);
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return chan->number | DMACH_LOW_LEVEL;
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}
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EXPORT_SYMBOL(s3c2410_dma_request);
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/* s3c2410_dma_free
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*
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* release the given channel back to the system, will stop and flush
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* any outstanding transfers, and ensure the channel is ready for the
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* next claimant.
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*
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* Note, although a warning is currently printed if the freeing client
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* info is not the same as the registrant's client info, the free is still
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* allowed to go through.
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*/
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int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client)
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{
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struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
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unsigned long flags;
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if (chan == NULL)
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return -EINVAL;
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local_irq_save(flags);
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if (chan->client != client) {
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printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
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channel, chan->client, client);
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}
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/* sort out stopping and freeing the channel */
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|
|
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chan->client = NULL;
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chan->in_use = 0;
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if (!(channel & DMACH_LOW_LEVEL))
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s3c_dma_chan_map[channel] = NULL;
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(s3c2410_dma_free);
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static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
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{
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struct s3c64xx_dmac *dmac = pw;
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struct s3c2410_dma_chan *chan;
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enum s3c2410_dma_buffresult res;
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u32 tcstat, errstat;
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u32 bit;
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int offs;
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tcstat = readl(dmac->regs + PL080_TC_STATUS);
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errstat = readl(dmac->regs + PL080_ERR_STATUS);
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for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) {
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struct s3c64xx_dma_buff *buff;
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if (!(errstat & bit) && !(tcstat & bit))
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continue;
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chan = dmac->channels + offs;
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res = S3C2410_RES_ERR;
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if (tcstat & bit) {
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writel(bit, dmac->regs + PL080_TC_CLEAR);
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res = S3C2410_RES_OK;
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}
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if (errstat & bit)
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writel(bit, dmac->regs + PL080_ERR_CLEAR);
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/* 'next' points to the buffer that is next to the
|
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* currently active buffer.
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* For CIRCULAR queues, 'next' will be same as 'curr'
|
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* when 'end' is the active buffer.
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*/
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buff = chan->curr;
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while (buff && buff != chan->next
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&& buff->next != chan->next)
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buff = buff->next;
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if (!buff)
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BUG();
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if (buff == chan->next)
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buff = chan->end;
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s3c64xx_dma_bufffdone(chan, buff, res);
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|
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/* Free the node and update curr, if non-circular queue */
|
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if (!(chan->flags & S3C2410_DMAF_CIRCULAR)) {
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chan->curr = buff->next;
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s3c64xx_dma_freebuff(buff);
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}
|
|
|
|
/* Update 'next' */
|
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buff = chan->next;
|
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if (chan->next == chan->end) {
|
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chan->next = chan->curr;
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if (!(chan->flags & S3C2410_DMAF_CIRCULAR))
|
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chan->end = NULL;
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} else {
|
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chan->next = buff->next;
|
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}
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static struct bus_type dma_subsys = {
|
|
.name = "s3c64xx-dma",
|
|
.dev_name = "s3c64xx-dma",
|
|
};
|
|
|
|
static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
|
|
int irq, unsigned int base)
|
|
{
|
|
struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
|
|
struct s3c64xx_dmac *dmac;
|
|
char clkname[16];
|
|
void __iomem *regs;
|
|
void __iomem *regptr;
|
|
int err, ch;
|
|
|
|
dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL);
|
|
if (!dmac) {
|
|
printk(KERN_ERR "%s: failed to alloc mem\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dmac->dev.id = chno / 8;
|
|
dmac->dev.bus = &dma_subsys;
|
|
|
|
err = device_register(&dmac->dev);
|
|
if (err) {
|
|
printk(KERN_ERR "%s: failed to register device\n", __func__);
|
|
goto err_alloc;
|
|
}
|
|
|
|
regs = ioremap(base, 0x200);
|
|
if (!regs) {
|
|
printk(KERN_ERR "%s: failed to ioremap()\n", __func__);
|
|
err = -ENXIO;
|
|
goto err_dev;
|
|
}
|
|
|
|
snprintf(clkname, sizeof(clkname), "dma%d", dmac->dev.id);
|
|
|
|
dmac->clk = clk_get(NULL, clkname);
|
|
if (IS_ERR(dmac->clk)) {
|
|
printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname);
|
|
err = PTR_ERR(dmac->clk);
|
|
goto err_map;
|
|
}
|
|
|
|
clk_prepare_enable(dmac->clk);
|
|
|
|
dmac->regs = regs;
|
|
dmac->chanbase = chbase;
|
|
dmac->channels = chptr;
|
|
|
|
err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac);
|
|
if (err < 0) {
|
|
printk(KERN_ERR "%s: failed to get irq\n", __func__);
|
|
goto err_clk;
|
|
}
|
|
|
|
regptr = regs + PL080_Cx_BASE(0);
|
|
|
|
for (ch = 0; ch < 8; ch++, chptr++) {
|
|
pr_debug("%s: registering DMA %d (%p)\n",
|
|
__func__, chno + ch, regptr);
|
|
|
|
chptr->bit = 1 << ch;
|
|
chptr->number = chno + ch;
|
|
chptr->dmac = dmac;
|
|
chptr->regs = regptr;
|
|
regptr += PL080_Cx_STRIDE;
|
|
}
|
|
|
|
/* for the moment, permanently enable the controller */
|
|
writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
|
|
|
|
printk(KERN_INFO "PL080: IRQ %d, at %p, channels %d..%d\n",
|
|
irq, regs, chno, chno+8);
|
|
|
|
return 0;
|
|
|
|
err_clk:
|
|
clk_disable_unprepare(dmac->clk);
|
|
clk_put(dmac->clk);
|
|
err_map:
|
|
iounmap(regs);
|
|
err_dev:
|
|
device_unregister(&dmac->dev);
|
|
err_alloc:
|
|
kfree(dmac);
|
|
return err;
|
|
}
|
|
|
|
static int __init s3c64xx_dma_init(void)
|
|
{
|
|
int ret;
|
|
|
|
/* This driver is not supported when booting with device tree. */
|
|
if (of_have_populated_dt())
|
|
return -ENODEV;
|
|
|
|
printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
|
|
|
|
dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0);
|
|
if (!dma_pool) {
|
|
printk(KERN_ERR "%s: failed to create pool\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = subsys_system_register(&dma_subsys, NULL);
|
|
if (ret) {
|
|
printk(KERN_ERR "%s: failed to create subsys\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Set all DMA configuration to be DMA, not SDMA */
|
|
writel(0xffffff, S3C64XX_SDMA_SEL);
|
|
|
|
/* Register standard DMA controllers */
|
|
s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
|
|
s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(s3c64xx_dma_init);
|