![Thierry Reding](/assets/img/avatar_default.png)
Add tegra_io_rail_power_off() and tegra_io_rail_power_on() functions to put IO rails into or out of deep powerdown mode, respectively. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
514 lines
11 KiB
C
514 lines
11 KiB
C
/*
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* drivers/powergate/tegra-powergate.c
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*
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* Copyright (c) 2010 Google, Inc
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/reset.h>
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#include <linux/seq_file.h>
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#include <linux/spinlock.h>
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#include <linux/clk/tegra.h>
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#include <linux/tegra-powergate.h>
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#include "fuse.h"
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#include "iomap.h"
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#define DPD_SAMPLE 0x020
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#define DPD_SAMPLE_ENABLE (1 << 0)
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#define DPD_SAMPLE_DISABLE (0 << 0)
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#define PWRGATE_TOGGLE 0x30
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#define PWRGATE_TOGGLE_START (1 << 8)
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#define REMOVE_CLAMPING 0x34
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#define PWRGATE_STATUS 0x38
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#define IO_DPD_REQ 0x1b8
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#define IO_DPD_REQ_CODE_IDLE (0 << 30)
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#define IO_DPD_REQ_CODE_OFF (1 << 30)
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#define IO_DPD_REQ_CODE_ON (2 << 30)
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#define IO_DPD_REQ_CODE_MASK (3 << 30)
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#define IO_DPD_STATUS 0x1bc
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#define IO_DPD2_REQ 0x1c0
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#define IO_DPD2_STATUS 0x1c4
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#define SEL_DPD_TIM 0x1c8
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#define GPU_RG_CNTRL 0x2d4
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static int tegra_num_powerdomains;
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static int tegra_num_cpu_domains;
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static const u8 *tegra_cpu_domains;
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static const u8 tegra30_cpu_domains[] = {
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TEGRA_POWERGATE_CPU,
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TEGRA_POWERGATE_CPU1,
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TEGRA_POWERGATE_CPU2,
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TEGRA_POWERGATE_CPU3,
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};
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static const u8 tegra114_cpu_domains[] = {
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TEGRA_POWERGATE_CPU0,
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TEGRA_POWERGATE_CPU1,
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TEGRA_POWERGATE_CPU2,
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TEGRA_POWERGATE_CPU3,
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};
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static const u8 tegra124_cpu_domains[] = {
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TEGRA_POWERGATE_CPU0,
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TEGRA_POWERGATE_CPU1,
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TEGRA_POWERGATE_CPU2,
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TEGRA_POWERGATE_CPU3,
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};
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static DEFINE_SPINLOCK(tegra_powergate_lock);
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static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
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static u32 pmc_read(unsigned long reg)
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{
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return readl(pmc + reg);
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}
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static void pmc_write(u32 val, unsigned long reg)
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{
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writel(val, pmc + reg);
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}
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static int tegra_powergate_set(int id, bool new_state)
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{
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bool status;
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unsigned long flags;
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spin_lock_irqsave(&tegra_powergate_lock, flags);
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status = pmc_read(PWRGATE_STATUS) & (1 << id);
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if (status == new_state) {
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spin_unlock_irqrestore(&tegra_powergate_lock, flags);
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return 0;
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}
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pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
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spin_unlock_irqrestore(&tegra_powergate_lock, flags);
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return 0;
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}
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int tegra_powergate_power_on(int id)
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{
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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return tegra_powergate_set(id, true);
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}
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int tegra_powergate_power_off(int id)
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{
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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return tegra_powergate_set(id, false);
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}
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EXPORT_SYMBOL(tegra_powergate_power_off);
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int tegra_powergate_is_powered(int id)
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{
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u32 status;
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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status = pmc_read(PWRGATE_STATUS) & (1 << id);
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return !!status;
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}
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int tegra_powergate_remove_clamping(int id)
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{
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u32 mask;
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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/*
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* The Tegra124 GPU has a separate register (with different semantics)
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* to remove clamps.
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*/
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if (tegra_chip_id == TEGRA124) {
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if (id == TEGRA_POWERGATE_3D) {
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pmc_write(0, GPU_RG_CNTRL);
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return 0;
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}
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}
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/*
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* Tegra 2 has a bug where PCIE and VDE clamping masks are
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* swapped relatively to the partition ids
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*/
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if (id == TEGRA_POWERGATE_VDEC)
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mask = (1 << TEGRA_POWERGATE_PCIE);
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else if (id == TEGRA_POWERGATE_PCIE)
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mask = (1 << TEGRA_POWERGATE_VDEC);
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else
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mask = (1 << id);
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pmc_write(mask, REMOVE_CLAMPING);
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return 0;
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}
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EXPORT_SYMBOL(tegra_powergate_remove_clamping);
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/* Must be called with clk disabled, and returns with clk enabled */
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int tegra_powergate_sequence_power_up(int id, struct clk *clk,
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struct reset_control *rst)
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{
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int ret;
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reset_control_assert(rst);
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ret = tegra_powergate_power_on(id);
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if (ret)
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goto err_power;
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ret = clk_prepare_enable(clk);
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if (ret)
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goto err_clk;
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udelay(10);
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ret = tegra_powergate_remove_clamping(id);
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if (ret)
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goto err_clamp;
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udelay(10);
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reset_control_deassert(rst);
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return 0;
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err_clamp:
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clk_disable_unprepare(clk);
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err_clk:
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tegra_powergate_power_off(id);
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err_power:
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return ret;
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}
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EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
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int tegra_cpu_powergate_id(int cpuid)
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{
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if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
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return tegra_cpu_domains[cpuid];
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return -EINVAL;
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}
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int __init tegra_powergate_init(void)
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{
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switch (tegra_chip_id) {
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case TEGRA20:
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tegra_num_powerdomains = 7;
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break;
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case TEGRA30:
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tegra_num_powerdomains = 14;
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tegra_num_cpu_domains = 4;
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tegra_cpu_domains = tegra30_cpu_domains;
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break;
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case TEGRA114:
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tegra_num_powerdomains = 23;
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tegra_num_cpu_domains = 4;
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tegra_cpu_domains = tegra114_cpu_domains;
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break;
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case TEGRA124:
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tegra_num_powerdomains = 25;
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tegra_num_cpu_domains = 4;
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tegra_cpu_domains = tegra124_cpu_domains;
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break;
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default:
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/* Unknown Tegra variant. Disable powergating */
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tegra_num_powerdomains = 0;
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break;
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}
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static const char * const *powergate_name;
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static const char * const powergate_name_t20[] = {
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[TEGRA_POWERGATE_CPU] = "cpu",
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[TEGRA_POWERGATE_3D] = "3d",
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[TEGRA_POWERGATE_VENC] = "venc",
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[TEGRA_POWERGATE_VDEC] = "vdec",
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[TEGRA_POWERGATE_PCIE] = "pcie",
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[TEGRA_POWERGATE_L2] = "l2",
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[TEGRA_POWERGATE_MPE] = "mpe",
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};
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static const char * const powergate_name_t30[] = {
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[TEGRA_POWERGATE_CPU] = "cpu0",
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[TEGRA_POWERGATE_3D] = "3d0",
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[TEGRA_POWERGATE_VENC] = "venc",
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[TEGRA_POWERGATE_VDEC] = "vdec",
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[TEGRA_POWERGATE_PCIE] = "pcie",
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[TEGRA_POWERGATE_L2] = "l2",
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[TEGRA_POWERGATE_MPE] = "mpe",
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[TEGRA_POWERGATE_HEG] = "heg",
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[TEGRA_POWERGATE_SATA] = "sata",
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[TEGRA_POWERGATE_CPU1] = "cpu1",
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[TEGRA_POWERGATE_CPU2] = "cpu2",
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[TEGRA_POWERGATE_CPU3] = "cpu3",
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[TEGRA_POWERGATE_CELP] = "celp",
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[TEGRA_POWERGATE_3D1] = "3d1",
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};
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static const char * const powergate_name_t114[] = {
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[TEGRA_POWERGATE_CPU] = "crail",
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[TEGRA_POWERGATE_3D] = "3d",
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[TEGRA_POWERGATE_VENC] = "venc",
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[TEGRA_POWERGATE_VDEC] = "vdec",
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[TEGRA_POWERGATE_MPE] = "mpe",
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[TEGRA_POWERGATE_HEG] = "heg",
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[TEGRA_POWERGATE_CPU1] = "cpu1",
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[TEGRA_POWERGATE_CPU2] = "cpu2",
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[TEGRA_POWERGATE_CPU3] = "cpu3",
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[TEGRA_POWERGATE_CELP] = "celp",
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[TEGRA_POWERGATE_CPU0] = "cpu0",
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[TEGRA_POWERGATE_C0NC] = "c0nc",
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[TEGRA_POWERGATE_C1NC] = "c1nc",
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[TEGRA_POWERGATE_DIS] = "dis",
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[TEGRA_POWERGATE_DISB] = "disb",
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[TEGRA_POWERGATE_XUSBA] = "xusba",
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[TEGRA_POWERGATE_XUSBB] = "xusbb",
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[TEGRA_POWERGATE_XUSBC] = "xusbc",
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};
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static const char * const powergate_name_t124[] = {
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[TEGRA_POWERGATE_CPU] = "crail",
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[TEGRA_POWERGATE_3D] = "3d",
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[TEGRA_POWERGATE_VENC] = "venc",
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[TEGRA_POWERGATE_PCIE] = "pcie",
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[TEGRA_POWERGATE_VDEC] = "vdec",
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[TEGRA_POWERGATE_L2] = "l2",
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[TEGRA_POWERGATE_MPE] = "mpe",
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[TEGRA_POWERGATE_HEG] = "heg",
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[TEGRA_POWERGATE_SATA] = "sata",
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[TEGRA_POWERGATE_CPU1] = "cpu1",
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[TEGRA_POWERGATE_CPU2] = "cpu2",
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[TEGRA_POWERGATE_CPU3] = "cpu3",
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[TEGRA_POWERGATE_CELP] = "celp",
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[TEGRA_POWERGATE_CPU0] = "cpu0",
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[TEGRA_POWERGATE_C0NC] = "c0nc",
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[TEGRA_POWERGATE_C1NC] = "c1nc",
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[TEGRA_POWERGATE_SOR] = "sor",
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[TEGRA_POWERGATE_DIS] = "dis",
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[TEGRA_POWERGATE_DISB] = "disb",
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[TEGRA_POWERGATE_XUSBA] = "xusba",
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[TEGRA_POWERGATE_XUSBB] = "xusbb",
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[TEGRA_POWERGATE_XUSBC] = "xusbc",
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[TEGRA_POWERGATE_VIC] = "vic",
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[TEGRA_POWERGATE_IRAM] = "iram",
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};
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static int powergate_show(struct seq_file *s, void *data)
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{
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int i;
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seq_printf(s, " powergate powered\n");
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seq_printf(s, "------------------\n");
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for (i = 0; i < tegra_num_powerdomains; i++) {
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if (!powergate_name[i])
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continue;
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seq_printf(s, " %9s %7s\n", powergate_name[i],
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tegra_powergate_is_powered(i) ? "yes" : "no");
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}
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return 0;
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}
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static int powergate_open(struct inode *inode, struct file *file)
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{
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return single_open(file, powergate_show, inode->i_private);
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}
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static const struct file_operations powergate_fops = {
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.open = powergate_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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int __init tegra_powergate_debugfs_init(void)
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{
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struct dentry *d;
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switch (tegra_chip_id) {
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case TEGRA20:
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powergate_name = powergate_name_t20;
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break;
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case TEGRA30:
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powergate_name = powergate_name_t30;
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break;
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case TEGRA114:
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powergate_name = powergate_name_t114;
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break;
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case TEGRA124:
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powergate_name = powergate_name_t124;
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break;
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}
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if (powergate_name) {
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d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
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&powergate_fops);
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if (!d)
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return -ENOMEM;
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}
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return 0;
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}
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#endif
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static int tegra_io_rail_prepare(int id, unsigned long *request,
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unsigned long *status, unsigned int *bit)
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{
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unsigned long rate, value;
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struct clk *clk;
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*bit = id % 32;
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/*
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* There are two sets of 30 bits to select IO rails, but bits 30 and
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* 31 are control bits rather than IO rail selection bits.
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*/
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if (id > 63 || *bit == 30 || *bit == 31)
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return -EINVAL;
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if (id < 32) {
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*status = IO_DPD_STATUS;
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*request = IO_DPD_REQ;
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} else {
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*status = IO_DPD2_STATUS;
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*request = IO_DPD2_REQ;
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}
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clk = clk_get_sys(NULL, "pclk");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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rate = clk_get_rate(clk);
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clk_put(clk);
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pmc_write(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
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/* must be at least 200 ns, in APB (PCLK) clock cycles */
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value = DIV_ROUND_UP(1000000000, rate);
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value = DIV_ROUND_UP(200, value);
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pmc_write(value, SEL_DPD_TIM);
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return 0;
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}
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static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
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unsigned long val, unsigned long timeout)
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{
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unsigned long value;
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timeout = jiffies + msecs_to_jiffies(timeout);
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while (time_after(timeout, jiffies)) {
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value = pmc_read(offset);
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if ((value & mask) == val)
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return 0;
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usleep_range(250, 1000);
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}
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return -ETIMEDOUT;
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}
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static void tegra_io_rail_unprepare(void)
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{
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pmc_write(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
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}
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int tegra_io_rail_power_on(int id)
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{
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unsigned long request, status, value;
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unsigned int bit, mask;
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int err;
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err = tegra_io_rail_prepare(id, &request, &status, &bit);
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if (err < 0)
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return err;
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mask = 1 << bit;
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value = pmc_read(request);
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value |= mask;
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value &= ~IO_DPD_REQ_CODE_MASK;
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value |= IO_DPD_REQ_CODE_OFF;
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pmc_write(value, request);
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err = tegra_io_rail_poll(status, mask, 0, 250);
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if (err < 0)
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return err;
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tegra_io_rail_unprepare();
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return 0;
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}
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int tegra_io_rail_power_off(int id)
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{
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unsigned long request, status, value;
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unsigned int bit, mask;
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int err;
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err = tegra_io_rail_prepare(id, &request, &status, &bit);
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if (err < 0)
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return err;
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mask = 1 << bit;
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value = pmc_read(request);
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value |= mask;
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value &= ~IO_DPD_REQ_CODE_MASK;
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value |= IO_DPD_REQ_CODE_ON;
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pmc_write(value, request);
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err = tegra_io_rail_poll(status, mask, mask, 250);
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if (err < 0)
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return err;
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|
tegra_io_rail_unprepare();
|
|
|
|
return 0;
|
|
}
|