![Robin Holt](/assets/img/avatar_default.png)
Preparing to move the parsing of reboot= to generic kernel code forces the change in reboot_mode handling to use the enum. [akpm@linux-foundation.org: fix arch/arm/mach-socfpga/socfpga.c] Signed-off-by: Robin Holt <holt@sgi.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Russ Anderson <rja@sgi.com> Cc: Robin Holt <holt@sgi.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
242 lines
5.6 KiB
C
242 lines
5.6 KiB
C
/*
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* linux/arch/arm/mach-w90x900/cpu.c
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*
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* Copyright (c) 2009 Nuvoton corporation.
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*
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* Wan ZongShun <mcuos.com@gmail.com>
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*
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* NUC900 series cpu common support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation;version 2 of the License.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/serial_8250.h>
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#include <linux/delay.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <asm/system_misc.h>
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#include <mach/hardware.h>
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#include <mach/regs-serial.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-ebi.h>
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#include <mach/regs-timer.h>
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#include "cpu.h"
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#include "clock.h"
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#include "nuc9xx.h"
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/* Initial IO mappings */
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static struct map_desc nuc900_iodesc[] __initdata = {
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IODESC_ENT(IRQ),
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IODESC_ENT(GCR),
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IODESC_ENT(UART),
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IODESC_ENT(TIMER),
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IODESC_ENT(EBI),
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IODESC_ENT(GPIO),
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};
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/* Initial clock declarations. */
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static DEFINE_CLK(lcd, 0);
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static DEFINE_CLK(audio, 1);
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static DEFINE_CLK(fmi, 4);
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static DEFINE_SUBCLK(ms, 0);
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static DEFINE_SUBCLK(sd, 1);
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static DEFINE_CLK(dmac, 5);
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static DEFINE_CLK(atapi, 6);
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static DEFINE_CLK(emc, 7);
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static DEFINE_SUBCLK(rmii, 2);
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static DEFINE_CLK(usbd, 8);
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static DEFINE_CLK(usbh, 9);
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static DEFINE_CLK(g2d, 10);
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static DEFINE_CLK(pwm, 18);
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static DEFINE_CLK(ps2, 24);
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static DEFINE_CLK(kpi, 25);
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static DEFINE_CLK(wdt, 26);
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static DEFINE_CLK(gdma, 27);
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static DEFINE_CLK(adc, 28);
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static DEFINE_CLK(usi, 29);
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static DEFINE_CLK(ext, 0);
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static DEFINE_CLK(timer0, 19);
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static DEFINE_CLK(timer1, 20);
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static DEFINE_CLK(timer2, 21);
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static DEFINE_CLK(timer3, 22);
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static DEFINE_CLK(timer4, 23);
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static struct clk_lookup nuc900_clkregs[] = {
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DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL),
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DEF_CLKLOOK(&clk_audio, "nuc900-ac97", NULL),
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DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL),
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DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"),
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DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"),
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DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL),
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DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL),
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DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL),
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DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"),
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DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL),
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DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL),
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DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL),
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DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL),
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DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL),
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DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
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DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
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DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
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DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL),
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DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
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DEF_CLKLOOK(&clk_ext, NULL, "ext"),
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DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),
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DEF_CLKLOOK(&clk_timer1, NULL, "timer1"),
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DEF_CLKLOOK(&clk_timer2, NULL, "timer2"),
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DEF_CLKLOOK(&clk_timer3, NULL, "timer3"),
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DEF_CLKLOOK(&clk_timer4, NULL, "timer4"),
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};
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/* Initial serial platform data */
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struct plat_serial8250_port nuc900_uart_data[] = {
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NUC900_8250PORT(UART0),
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{},
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};
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struct platform_device nuc900_serial_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = nuc900_uart_data,
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},
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};
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/*Set NUC900 series cpu frequence*/
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static int __init nuc900_set_clkval(unsigned int cpufreq)
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{
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unsigned int pllclk, ahbclk, apbclk, val;
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pllclk = 0;
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ahbclk = 0;
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apbclk = 0;
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switch (cpufreq) {
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case 66:
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pllclk = PLL_66MHZ;
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ahbclk = AHB_CPUCLK_1_1;
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apbclk = APB_AHB_1_2;
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break;
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case 100:
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pllclk = PLL_100MHZ;
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ahbclk = AHB_CPUCLK_1_1;
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apbclk = APB_AHB_1_2;
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break;
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case 120:
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pllclk = PLL_120MHZ;
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ahbclk = AHB_CPUCLK_1_2;
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apbclk = APB_AHB_1_2;
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break;
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case 166:
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pllclk = PLL_166MHZ;
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ahbclk = AHB_CPUCLK_1_2;
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apbclk = APB_AHB_1_2;
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break;
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case 200:
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pllclk = PLL_200MHZ;
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ahbclk = AHB_CPUCLK_1_2;
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apbclk = APB_AHB_1_2;
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break;
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}
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__raw_writel(pllclk, REG_PLLCON0);
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val = __raw_readl(REG_CLKDIV);
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val &= ~(0x03 << 24 | 0x03 << 26);
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val |= (ahbclk << 24 | apbclk << 26);
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__raw_writel(val, REG_CLKDIV);
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return 0;
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}
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static int __init nuc900_set_cpufreq(char *str)
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{
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unsigned long cpufreq, val;
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if (!*str)
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return 0;
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strict_strtoul(str, 0, &cpufreq);
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nuc900_clock_source(NULL, "ext");
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nuc900_set_clkval(cpufreq);
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mdelay(1);
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val = __raw_readl(REG_CKSKEW);
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val &= ~0xff;
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val |= DEFAULTSKEW;
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__raw_writel(val, REG_CKSKEW);
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nuc900_clock_source(NULL, "pll0");
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return 1;
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}
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__setup("cpufreq=", nuc900_set_cpufreq);
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/*Init NUC900 evb io*/
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void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
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{
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unsigned long idcode = 0x0;
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iotable_init(mach_desc, mach_size);
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iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc));
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idcode = __raw_readl(NUC900PDID);
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if (idcode == NUC910_CPUID)
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printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
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else if (idcode == NUC920_CPUID)
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printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode);
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else if (idcode == NUC950_CPUID)
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printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode);
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else if (idcode == NUC960_CPUID)
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printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode);
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}
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/*Init NUC900 clock*/
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void __init nuc900_init_clocks(void)
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{
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clkdev_add_table(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
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}
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#define WTCR (TMR_BA + 0x1C)
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#define WTCLK (1 << 10)
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#define WTE (1 << 7)
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#define WTRE (1 << 1)
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void nuc9xx_restart(enum reboot_mode mode, const char *cmd)
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{
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if (mode == REBOOT_SOFT) {
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/* Jump into ROM at address 0 */
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soft_restart(0);
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} else {
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__raw_writel(WTE | WTRE | WTCLK, WTCR);
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}
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}
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