![Russell King](/assets/img/avatar_default.png)
Peter reports that OMAP audio broke with the recent fix for these checks, caused by OMAP audio using a 64-bit DMA mask. We should allow 64-bit DMA masks even with 32-bit dma_addr_t if we can be sure the amount of RAM we have won't allow the 32-bit dma_addr_t to overflow. Unfortunately, the checks to detect overflow were not correct. Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2001 lines
52 KiB
C
2001 lines
52 KiB
C
/*
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* linux/arch/arm/mm/dma-mapping.c
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*
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* Copyright (C) 2000-2004 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* DMA uncached mapping support.
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*/
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#include <linux/bootmem.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/gfp.h>
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#include <linux/errno.h>
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#include <linux/list.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-contiguous.h>
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#include <linux/highmem.h>
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#include <linux/memblock.h>
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#include <linux/slab.h>
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#include <linux/iommu.h>
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#include <linux/io.h>
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#include <linux/vmalloc.h>
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#include <linux/sizes.h>
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#include <asm/memory.h>
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#include <asm/highmem.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/mach/arch.h>
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#include <asm/dma-iommu.h>
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#include <asm/mach/map.h>
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#include <asm/system_info.h>
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#include <asm/dma-contiguous.h>
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#include "mm.h"
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/*
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* The DMA API is built upon the notion of "buffer ownership". A buffer
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* is either exclusively owned by the CPU (and therefore may be accessed
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* by it) or exclusively owned by the DMA device. These helper functions
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* represent the transitions between these two ownership states.
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*
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* Note, however, that on later ARMs, this notion does not work due to
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* speculative prefetches. We model our approach on the assumption that
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* the CPU does do speculative prefetches, which means we clean caches
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* before transfers and delay cache invalidation until transfer completion.
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*
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*/
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static void __dma_page_cpu_to_dev(struct page *, unsigned long,
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size_t, enum dma_data_direction);
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static void __dma_page_dev_to_cpu(struct page *, unsigned long,
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size_t, enum dma_data_direction);
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/**
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* arm_dma_map_page - map a portion of a page for streaming DMA
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @page: page that buffer resides in
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* @offset: offset into page for start of buffer
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* @size: size of buffer to map
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* @dir: DMA transfer direction
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*
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* Ensure that any data held in the cache is appropriately discarded
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* or written back.
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*
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* The device owns this memory once this call has completed. The CPU
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* can regain ownership by calling dma_unmap_page().
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*/
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static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
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__dma_page_cpu_to_dev(page, offset, size, dir);
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return pfn_to_dma(dev, page_to_pfn(page)) + offset;
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}
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static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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return pfn_to_dma(dev, page_to_pfn(page)) + offset;
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}
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/**
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* arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @handle: DMA address of buffer
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* @size: size of buffer (same as passed to dma_map_page)
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* @dir: DMA transfer direction (same as passed to dma_map_page)
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*
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* Unmap a page streaming mode DMA translation. The handle and size
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* must match what was provided in the previous dma_map_page() call.
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* All other usages are undefined.
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*
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* After this call, reads by the CPU to the buffer are guaranteed to see
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* whatever the device wrote there.
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*/
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static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
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size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
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__dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
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handle & ~PAGE_MASK, size, dir);
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}
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static void arm_dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t handle, size_t size, enum dma_data_direction dir)
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{
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unsigned int offset = handle & (PAGE_SIZE - 1);
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struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
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__dma_page_dev_to_cpu(page, offset, size, dir);
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}
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static void arm_dma_sync_single_for_device(struct device *dev,
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dma_addr_t handle, size_t size, enum dma_data_direction dir)
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{
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unsigned int offset = handle & (PAGE_SIZE - 1);
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struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
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__dma_page_cpu_to_dev(page, offset, size, dir);
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}
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struct dma_map_ops arm_dma_ops = {
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.alloc = arm_dma_alloc,
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.free = arm_dma_free,
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.mmap = arm_dma_mmap,
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.get_sgtable = arm_dma_get_sgtable,
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.map_page = arm_dma_map_page,
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.unmap_page = arm_dma_unmap_page,
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.map_sg = arm_dma_map_sg,
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.unmap_sg = arm_dma_unmap_sg,
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.sync_single_for_cpu = arm_dma_sync_single_for_cpu,
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.sync_single_for_device = arm_dma_sync_single_for_device,
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.sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
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.sync_sg_for_device = arm_dma_sync_sg_for_device,
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.set_dma_mask = arm_dma_set_mask,
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};
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EXPORT_SYMBOL(arm_dma_ops);
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static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
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dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
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static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t handle, struct dma_attrs *attrs);
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struct dma_map_ops arm_coherent_dma_ops = {
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.alloc = arm_coherent_dma_alloc,
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.free = arm_coherent_dma_free,
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.mmap = arm_dma_mmap,
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.get_sgtable = arm_dma_get_sgtable,
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.map_page = arm_coherent_dma_map_page,
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.map_sg = arm_dma_map_sg,
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.set_dma_mask = arm_dma_set_mask,
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};
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EXPORT_SYMBOL(arm_coherent_dma_ops);
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static int __dma_supported(struct device *dev, u64 mask, bool warn)
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{
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unsigned long max_dma_pfn;
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/*
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* If the mask allows for more memory than we can address,
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* and we actually have that much memory, then we must
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* indicate that DMA to this device is not supported.
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*/
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if (sizeof(mask) != sizeof(dma_addr_t) &&
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mask > (dma_addr_t)~0 &&
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dma_to_pfn(dev, ~0) < max_pfn) {
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if (warn) {
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dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
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mask);
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dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
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}
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return 0;
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}
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max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
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/*
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* Translate the device's DMA mask to a PFN limit. This
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* PFN number includes the page which we can DMA to.
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*/
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if (dma_to_pfn(dev, mask) < max_dma_pfn) {
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if (warn)
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dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
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mask,
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dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
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max_dma_pfn + 1);
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return 0;
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}
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return 1;
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}
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static u64 get_coherent_dma_mask(struct device *dev)
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{
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u64 mask = (u64)DMA_BIT_MASK(32);
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if (dev) {
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mask = dev->coherent_dma_mask;
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/*
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* Sanity check the DMA mask - it must be non-zero, and
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* must be able to be satisfied by a DMA allocation.
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*/
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if (mask == 0) {
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dev_warn(dev, "coherent DMA mask is unset\n");
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return 0;
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}
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if (!__dma_supported(dev, mask, true))
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return 0;
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}
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return mask;
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}
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static void __dma_clear_buffer(struct page *page, size_t size)
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{
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/*
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* Ensure that the allocated pages are zeroed, and that any data
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* lurking in the kernel direct-mapped region is invalidated.
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*/
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if (PageHighMem(page)) {
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phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
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phys_addr_t end = base + size;
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while (size > 0) {
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void *ptr = kmap_atomic(page);
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memset(ptr, 0, PAGE_SIZE);
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dmac_flush_range(ptr, ptr + PAGE_SIZE);
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kunmap_atomic(ptr);
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page++;
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size -= PAGE_SIZE;
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}
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outer_flush_range(base, end);
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} else {
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void *ptr = page_address(page);
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memset(ptr, 0, size);
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dmac_flush_range(ptr, ptr + size);
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outer_flush_range(__pa(ptr), __pa(ptr) + size);
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}
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}
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/*
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* Allocate a DMA buffer for 'dev' of size 'size' using the
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* specified gfp mask. Note that 'size' must be page aligned.
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*/
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static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
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{
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unsigned long order = get_order(size);
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struct page *page, *p, *e;
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page = alloc_pages(gfp, order);
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if (!page)
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return NULL;
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/*
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* Now split the huge page and free the excess pages
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*/
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split_page(page, order);
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for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
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__free_page(p);
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__dma_clear_buffer(page, size);
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return page;
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}
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/*
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* Free a DMA buffer. 'size' must be page aligned.
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*/
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static void __dma_free_buffer(struct page *page, size_t size)
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{
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struct page *e = page + (size >> PAGE_SHIFT);
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while (page < e) {
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__free_page(page);
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page++;
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}
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}
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#ifdef CONFIG_MMU
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#ifdef CONFIG_HUGETLB_PAGE
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#warning ARM Coherent DMA allocator does not (yet) support huge TLB
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#endif
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static void *__alloc_from_contiguous(struct device *dev, size_t size,
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pgprot_t prot, struct page **ret_page,
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const void *caller);
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static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
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pgprot_t prot, struct page **ret_page,
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const void *caller);
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static void *
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__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
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const void *caller)
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{
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struct vm_struct *area;
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unsigned long addr;
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/*
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* DMA allocation can be mapped to user space, so lets
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* set VM_USERMAP flags too.
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*/
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area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
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caller);
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if (!area)
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return NULL;
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addr = (unsigned long)area->addr;
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area->phys_addr = __pfn_to_phys(page_to_pfn(page));
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if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
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vunmap((void *)addr);
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return NULL;
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}
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return (void *)addr;
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}
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static void __dma_free_remap(void *cpu_addr, size_t size)
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{
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unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
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struct vm_struct *area = find_vm_area(cpu_addr);
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if (!area || (area->flags & flags) != flags) {
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WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
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return;
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}
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unmap_kernel_range((unsigned long)cpu_addr, size);
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vunmap(cpu_addr);
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}
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#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
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struct dma_pool {
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size_t size;
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spinlock_t lock;
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unsigned long *bitmap;
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unsigned long nr_pages;
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void *vaddr;
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struct page **pages;
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};
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static struct dma_pool atomic_pool = {
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.size = DEFAULT_DMA_COHERENT_POOL_SIZE,
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};
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static int __init early_coherent_pool(char *p)
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{
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atomic_pool.size = memparse(p, &p);
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return 0;
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}
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early_param("coherent_pool", early_coherent_pool);
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void __init init_dma_coherent_pool_size(unsigned long size)
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{
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/*
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* Catch any attempt to set the pool size too late.
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*/
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BUG_ON(atomic_pool.vaddr);
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/*
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* Set architecture specific coherent pool size only if
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* it has not been changed by kernel command line parameter.
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*/
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if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
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atomic_pool.size = size;
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}
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/*
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* Initialise the coherent pool for atomic allocations.
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*/
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static int __init atomic_pool_init(void)
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{
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struct dma_pool *pool = &atomic_pool;
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pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
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gfp_t gfp = GFP_KERNEL | GFP_DMA;
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unsigned long nr_pages = pool->size >> PAGE_SHIFT;
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unsigned long *bitmap;
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struct page *page;
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struct page **pages;
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void *ptr;
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int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
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bitmap = kzalloc(bitmap_size, GFP_KERNEL);
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if (!bitmap)
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goto no_bitmap;
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pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
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if (!pages)
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goto no_pages;
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if (IS_ENABLED(CONFIG_DMA_CMA))
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ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
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atomic_pool_init);
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else
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ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
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atomic_pool_init);
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if (ptr) {
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int i;
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for (i = 0; i < nr_pages; i++)
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pages[i] = page + i;
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spin_lock_init(&pool->lock);
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pool->vaddr = ptr;
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pool->pages = pages;
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pool->bitmap = bitmap;
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pool->nr_pages = nr_pages;
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pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
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(unsigned)pool->size / 1024);
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return 0;
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}
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kfree(pages);
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no_pages:
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kfree(bitmap);
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no_bitmap:
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pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
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(unsigned)pool->size / 1024);
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return -ENOMEM;
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}
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/*
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* CMA is activated by core_initcall, so we must be called after it.
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*/
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postcore_initcall(atomic_pool_init);
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struct dma_contig_early_reserve {
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phys_addr_t base;
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unsigned long size;
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};
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static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
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static int dma_mmu_remap_num __initdata;
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void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
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{
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dma_mmu_remap[dma_mmu_remap_num].base = base;
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dma_mmu_remap[dma_mmu_remap_num].size = size;
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dma_mmu_remap_num++;
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}
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void __init dma_contiguous_remap(void)
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{
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int i;
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for (i = 0; i < dma_mmu_remap_num; i++) {
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phys_addr_t start = dma_mmu_remap[i].base;
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phys_addr_t end = start + dma_mmu_remap[i].size;
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struct map_desc map;
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unsigned long addr;
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if (end > arm_lowmem_limit)
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end = arm_lowmem_limit;
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if (start >= end)
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continue;
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map.pfn = __phys_to_pfn(start);
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map.virtual = __phys_to_virt(start);
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map.length = end - start;
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map.type = MT_MEMORY_DMA_READY;
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/*
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* Clear previous low-memory mapping
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*/
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for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
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addr += PMD_SIZE)
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pmd_clear(pmd_off_k(addr));
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iotable_init(&map, 1);
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}
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}
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static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
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void *data)
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{
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struct page *page = virt_to_page(addr);
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pgprot_t prot = *(pgprot_t *)data;
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|
|
set_pte_ext(pte, mk_pte(page, prot), 0);
|
|
return 0;
|
|
}
|
|
|
|
static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
|
|
{
|
|
unsigned long start = (unsigned long) page_address(page);
|
|
unsigned end = start + size;
|
|
|
|
apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
|
|
flush_tlb_kernel_range(start, end);
|
|
}
|
|
|
|
static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
|
|
pgprot_t prot, struct page **ret_page,
|
|
const void *caller)
|
|
{
|
|
struct page *page;
|
|
void *ptr;
|
|
page = __dma_alloc_buffer(dev, size, gfp);
|
|
if (!page)
|
|
return NULL;
|
|
|
|
ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
|
|
if (!ptr) {
|
|
__dma_free_buffer(page, size);
|
|
return NULL;
|
|
}
|
|
|
|
*ret_page = page;
|
|
return ptr;
|
|
}
|
|
|
|
static void *__alloc_from_pool(size_t size, struct page **ret_page)
|
|
{
|
|
struct dma_pool *pool = &atomic_pool;
|
|
unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
|
unsigned int pageno;
|
|
unsigned long flags;
|
|
void *ptr = NULL;
|
|
unsigned long align_mask;
|
|
|
|
if (!pool->vaddr) {
|
|
WARN(1, "coherent pool not initialised!\n");
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Align the region allocation - allocations from pool are rather
|
|
* small, so align them to their order in pages, minimum is a page
|
|
* size. This helps reduce fragmentation of the DMA space.
|
|
*/
|
|
align_mask = (1 << get_order(size)) - 1;
|
|
|
|
spin_lock_irqsave(&pool->lock, flags);
|
|
pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
|
|
0, count, align_mask);
|
|
if (pageno < pool->nr_pages) {
|
|
bitmap_set(pool->bitmap, pageno, count);
|
|
ptr = pool->vaddr + PAGE_SIZE * pageno;
|
|
*ret_page = pool->pages[pageno];
|
|
} else {
|
|
pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
|
|
"Please increase it with coherent_pool= kernel parameter!\n",
|
|
(unsigned)pool->size / 1024);
|
|
}
|
|
spin_unlock_irqrestore(&pool->lock, flags);
|
|
|
|
return ptr;
|
|
}
|
|
|
|
static bool __in_atomic_pool(void *start, size_t size)
|
|
{
|
|
struct dma_pool *pool = &atomic_pool;
|
|
void *end = start + size;
|
|
void *pool_start = pool->vaddr;
|
|
void *pool_end = pool->vaddr + pool->size;
|
|
|
|
if (start < pool_start || start >= pool_end)
|
|
return false;
|
|
|
|
if (end <= pool_end)
|
|
return true;
|
|
|
|
WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
|
|
start, end - 1, pool_start, pool_end - 1);
|
|
|
|
return false;
|
|
}
|
|
|
|
static int __free_from_pool(void *start, size_t size)
|
|
{
|
|
struct dma_pool *pool = &atomic_pool;
|
|
unsigned long pageno, count;
|
|
unsigned long flags;
|
|
|
|
if (!__in_atomic_pool(start, size))
|
|
return 0;
|
|
|
|
pageno = (start - pool->vaddr) >> PAGE_SHIFT;
|
|
count = size >> PAGE_SHIFT;
|
|
|
|
spin_lock_irqsave(&pool->lock, flags);
|
|
bitmap_clear(pool->bitmap, pageno, count);
|
|
spin_unlock_irqrestore(&pool->lock, flags);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void *__alloc_from_contiguous(struct device *dev, size_t size,
|
|
pgprot_t prot, struct page **ret_page,
|
|
const void *caller)
|
|
{
|
|
unsigned long order = get_order(size);
|
|
size_t count = size >> PAGE_SHIFT;
|
|
struct page *page;
|
|
void *ptr;
|
|
|
|
page = dma_alloc_from_contiguous(dev, count, order);
|
|
if (!page)
|
|
return NULL;
|
|
|
|
__dma_clear_buffer(page, size);
|
|
|
|
if (PageHighMem(page)) {
|
|
ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
|
|
if (!ptr) {
|
|
dma_release_from_contiguous(dev, page, count);
|
|
return NULL;
|
|
}
|
|
} else {
|
|
__dma_remap(page, size, prot);
|
|
ptr = page_address(page);
|
|
}
|
|
*ret_page = page;
|
|
return ptr;
|
|
}
|
|
|
|
static void __free_from_contiguous(struct device *dev, struct page *page,
|
|
void *cpu_addr, size_t size)
|
|
{
|
|
if (PageHighMem(page))
|
|
__dma_free_remap(cpu_addr, size);
|
|
else
|
|
__dma_remap(page, size, pgprot_kernel);
|
|
dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
|
|
}
|
|
|
|
static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
|
|
{
|
|
prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
|
|
pgprot_writecombine(prot) :
|
|
pgprot_dmacoherent(prot);
|
|
return prot;
|
|
}
|
|
|
|
#define nommu() 0
|
|
|
|
#else /* !CONFIG_MMU */
|
|
|
|
#define nommu() 1
|
|
|
|
#define __get_dma_pgprot(attrs, prot) __pgprot(0)
|
|
#define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
|
|
#define __alloc_from_pool(size, ret_page) NULL
|
|
#define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
|
|
#define __free_from_pool(cpu_addr, size) 0
|
|
#define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
|
|
#define __dma_free_remap(cpu_addr, size) do { } while (0)
|
|
|
|
#endif /* CONFIG_MMU */
|
|
|
|
static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
|
|
struct page **ret_page)
|
|
{
|
|
struct page *page;
|
|
page = __dma_alloc_buffer(dev, size, gfp);
|
|
if (!page)
|
|
return NULL;
|
|
|
|
*ret_page = page;
|
|
return page_address(page);
|
|
}
|
|
|
|
|
|
|
|
static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
|
|
gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
|
|
{
|
|
u64 mask = get_coherent_dma_mask(dev);
|
|
struct page *page = NULL;
|
|
void *addr;
|
|
|
|
#ifdef CONFIG_DMA_API_DEBUG
|
|
u64 limit = (mask + 1) & ~mask;
|
|
if (limit && size >= limit) {
|
|
dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
|
|
size, mask);
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
if (!mask)
|
|
return NULL;
|
|
|
|
if (mask < 0xffffffffULL)
|
|
gfp |= GFP_DMA;
|
|
|
|
/*
|
|
* Following is a work-around (a.k.a. hack) to prevent pages
|
|
* with __GFP_COMP being passed to split_page() which cannot
|
|
* handle them. The real problem is that this flag probably
|
|
* should be 0 on ARM as it is not supported on this
|
|
* platform; see CONFIG_HUGETLBFS.
|
|
*/
|
|
gfp &= ~(__GFP_COMP);
|
|
|
|
*handle = DMA_ERROR_CODE;
|
|
size = PAGE_ALIGN(size);
|
|
|
|
if (is_coherent || nommu())
|
|
addr = __alloc_simple_buffer(dev, size, gfp, &page);
|
|
else if (!(gfp & __GFP_WAIT))
|
|
addr = __alloc_from_pool(size, &page);
|
|
else if (!IS_ENABLED(CONFIG_DMA_CMA))
|
|
addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
|
|
else
|
|
addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
|
|
|
|
if (addr)
|
|
*handle = pfn_to_dma(dev, page_to_pfn(page));
|
|
|
|
return addr;
|
|
}
|
|
|
|
/*
|
|
* Allocate DMA-coherent memory space and return both the kernel remapped
|
|
* virtual and bus address for that space.
|
|
*/
|
|
void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
|
|
gfp_t gfp, struct dma_attrs *attrs)
|
|
{
|
|
pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
|
|
void *memory;
|
|
|
|
if (dma_alloc_from_coherent(dev, size, handle, &memory))
|
|
return memory;
|
|
|
|
return __dma_alloc(dev, size, handle, gfp, prot, false,
|
|
__builtin_return_address(0));
|
|
}
|
|
|
|
static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
|
|
dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
|
|
{
|
|
pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
|
|
void *memory;
|
|
|
|
if (dma_alloc_from_coherent(dev, size, handle, &memory))
|
|
return memory;
|
|
|
|
return __dma_alloc(dev, size, handle, gfp, prot, true,
|
|
__builtin_return_address(0));
|
|
}
|
|
|
|
/*
|
|
* Create userspace mapping for the DMA-coherent memory.
|
|
*/
|
|
int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
|
|
void *cpu_addr, dma_addr_t dma_addr, size_t size,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
int ret = -ENXIO;
|
|
#ifdef CONFIG_MMU
|
|
unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
|
|
unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
|
unsigned long pfn = dma_to_pfn(dev, dma_addr);
|
|
unsigned long off = vma->vm_pgoff;
|
|
|
|
vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
|
|
|
|
if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
|
|
return ret;
|
|
|
|
if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
|
|
ret = remap_pfn_range(vma, vma->vm_start,
|
|
pfn + off,
|
|
vma->vm_end - vma->vm_start,
|
|
vma->vm_page_prot);
|
|
}
|
|
#endif /* CONFIG_MMU */
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Free a buffer as defined by the above mapping.
|
|
*/
|
|
static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
|
|
dma_addr_t handle, struct dma_attrs *attrs,
|
|
bool is_coherent)
|
|
{
|
|
struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
|
|
|
|
if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
|
|
return;
|
|
|
|
size = PAGE_ALIGN(size);
|
|
|
|
if (is_coherent || nommu()) {
|
|
__dma_free_buffer(page, size);
|
|
} else if (__free_from_pool(cpu_addr, size)) {
|
|
return;
|
|
} else if (!IS_ENABLED(CONFIG_DMA_CMA)) {
|
|
__dma_free_remap(cpu_addr, size);
|
|
__dma_free_buffer(page, size);
|
|
} else {
|
|
/*
|
|
* Non-atomic allocations cannot be freed with IRQs disabled
|
|
*/
|
|
WARN_ON(irqs_disabled());
|
|
__free_from_contiguous(dev, page, cpu_addr, size);
|
|
}
|
|
}
|
|
|
|
void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
|
|
dma_addr_t handle, struct dma_attrs *attrs)
|
|
{
|
|
__arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
|
|
}
|
|
|
|
static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
|
|
dma_addr_t handle, struct dma_attrs *attrs)
|
|
{
|
|
__arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
|
|
}
|
|
|
|
int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
|
|
void *cpu_addr, dma_addr_t handle, size_t size,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
|
|
int ret;
|
|
|
|
ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
|
|
if (unlikely(ret))
|
|
return ret;
|
|
|
|
sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
|
|
return 0;
|
|
}
|
|
|
|
static void dma_cache_maint_page(struct page *page, unsigned long offset,
|
|
size_t size, enum dma_data_direction dir,
|
|
void (*op)(const void *, size_t, int))
|
|
{
|
|
unsigned long pfn;
|
|
size_t left = size;
|
|
|
|
pfn = page_to_pfn(page) + offset / PAGE_SIZE;
|
|
offset %= PAGE_SIZE;
|
|
|
|
/*
|
|
* A single sg entry may refer to multiple physically contiguous
|
|
* pages. But we still need to process highmem pages individually.
|
|
* If highmem is not configured then the bulk of this loop gets
|
|
* optimized out.
|
|
*/
|
|
do {
|
|
size_t len = left;
|
|
void *vaddr;
|
|
|
|
page = pfn_to_page(pfn);
|
|
|
|
if (PageHighMem(page)) {
|
|
if (len + offset > PAGE_SIZE)
|
|
len = PAGE_SIZE - offset;
|
|
|
|
if (cache_is_vipt_nonaliasing()) {
|
|
vaddr = kmap_atomic(page);
|
|
op(vaddr + offset, len, dir);
|
|
kunmap_atomic(vaddr);
|
|
} else {
|
|
vaddr = kmap_high_get(page);
|
|
if (vaddr) {
|
|
op(vaddr + offset, len, dir);
|
|
kunmap_high(page);
|
|
}
|
|
}
|
|
} else {
|
|
vaddr = page_address(page) + offset;
|
|
op(vaddr, len, dir);
|
|
}
|
|
offset = 0;
|
|
pfn++;
|
|
left -= len;
|
|
} while (left);
|
|
}
|
|
|
|
/*
|
|
* Make an area consistent for devices.
|
|
* Note: Drivers should NOT use this function directly, as it will break
|
|
* platforms with CONFIG_DMABOUNCE.
|
|
* Use the driver DMA support - see dma-mapping.h (dma_sync_*)
|
|
*/
|
|
static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
|
|
size_t size, enum dma_data_direction dir)
|
|
{
|
|
unsigned long paddr;
|
|
|
|
dma_cache_maint_page(page, off, size, dir, dmac_map_area);
|
|
|
|
paddr = page_to_phys(page) + off;
|
|
if (dir == DMA_FROM_DEVICE) {
|
|
outer_inv_range(paddr, paddr + size);
|
|
} else {
|
|
outer_clean_range(paddr, paddr + size);
|
|
}
|
|
/* FIXME: non-speculating: flush on bidirectional mappings? */
|
|
}
|
|
|
|
static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
|
|
size_t size, enum dma_data_direction dir)
|
|
{
|
|
unsigned long paddr = page_to_phys(page) + off;
|
|
|
|
/* FIXME: non-speculating: not required */
|
|
/* don't bother invalidating if DMA to device */
|
|
if (dir != DMA_TO_DEVICE)
|
|
outer_inv_range(paddr, paddr + size);
|
|
|
|
dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
|
|
|
|
/*
|
|
* Mark the D-cache clean for these pages to avoid extra flushing.
|
|
*/
|
|
if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
|
|
unsigned long pfn;
|
|
size_t left = size;
|
|
|
|
pfn = page_to_pfn(page) + off / PAGE_SIZE;
|
|
off %= PAGE_SIZE;
|
|
if (off) {
|
|
pfn++;
|
|
left -= PAGE_SIZE - off;
|
|
}
|
|
while (left >= PAGE_SIZE) {
|
|
page = pfn_to_page(pfn++);
|
|
set_bit(PG_dcache_clean, &page->flags);
|
|
left -= PAGE_SIZE;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
|
|
* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
|
|
* @sg: list of buffers
|
|
* @nents: number of buffers to map
|
|
* @dir: DMA transfer direction
|
|
*
|
|
* Map a set of buffers described by scatterlist in streaming mode for DMA.
|
|
* This is the scatter-gather version of the dma_map_single interface.
|
|
* Here the scatter gather list elements are each tagged with the
|
|
* appropriate dma address and length. They are obtained via
|
|
* sg_dma_{address,length}.
|
|
*
|
|
* Device ownership issues as mentioned for dma_map_single are the same
|
|
* here.
|
|
*/
|
|
int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
|
|
enum dma_data_direction dir, struct dma_attrs *attrs)
|
|
{
|
|
struct dma_map_ops *ops = get_dma_ops(dev);
|
|
struct scatterlist *s;
|
|
int i, j;
|
|
|
|
for_each_sg(sg, s, nents, i) {
|
|
#ifdef CONFIG_NEED_SG_DMA_LENGTH
|
|
s->dma_length = s->length;
|
|
#endif
|
|
s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
|
|
s->length, dir, attrs);
|
|
if (dma_mapping_error(dev, s->dma_address))
|
|
goto bad_mapping;
|
|
}
|
|
return nents;
|
|
|
|
bad_mapping:
|
|
for_each_sg(sg, s, i, j)
|
|
ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
|
|
* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
|
|
* @sg: list of buffers
|
|
* @nents: number of buffers to unmap (same as was passed to dma_map_sg)
|
|
* @dir: DMA transfer direction (same as was passed to dma_map_sg)
|
|
*
|
|
* Unmap a set of streaming mode DMA translations. Again, CPU access
|
|
* rules concerning calls here are the same as for dma_unmap_single().
|
|
*/
|
|
void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
|
|
enum dma_data_direction dir, struct dma_attrs *attrs)
|
|
{
|
|
struct dma_map_ops *ops = get_dma_ops(dev);
|
|
struct scatterlist *s;
|
|
|
|
int i;
|
|
|
|
for_each_sg(sg, s, nents, i)
|
|
ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
|
|
}
|
|
|
|
/**
|
|
* arm_dma_sync_sg_for_cpu
|
|
* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
|
|
* @sg: list of buffers
|
|
* @nents: number of buffers to map (returned from dma_map_sg)
|
|
* @dir: DMA transfer direction (same as was passed to dma_map_sg)
|
|
*/
|
|
void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
|
|
int nents, enum dma_data_direction dir)
|
|
{
|
|
struct dma_map_ops *ops = get_dma_ops(dev);
|
|
struct scatterlist *s;
|
|
int i;
|
|
|
|
for_each_sg(sg, s, nents, i)
|
|
ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
|
|
dir);
|
|
}
|
|
|
|
/**
|
|
* arm_dma_sync_sg_for_device
|
|
* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
|
|
* @sg: list of buffers
|
|
* @nents: number of buffers to map (returned from dma_map_sg)
|
|
* @dir: DMA transfer direction (same as was passed to dma_map_sg)
|
|
*/
|
|
void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
|
|
int nents, enum dma_data_direction dir)
|
|
{
|
|
struct dma_map_ops *ops = get_dma_ops(dev);
|
|
struct scatterlist *s;
|
|
int i;
|
|
|
|
for_each_sg(sg, s, nents, i)
|
|
ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
|
|
dir);
|
|
}
|
|
|
|
/*
|
|
* Return whether the given device DMA address mask can be supported
|
|
* properly. For example, if your device can only drive the low 24-bits
|
|
* during bus mastering, then you would pass 0x00ffffff as the mask
|
|
* to this function.
|
|
*/
|
|
int dma_supported(struct device *dev, u64 mask)
|
|
{
|
|
return __dma_supported(dev, mask, false);
|
|
}
|
|
EXPORT_SYMBOL(dma_supported);
|
|
|
|
int arm_dma_set_mask(struct device *dev, u64 dma_mask)
|
|
{
|
|
if (!dev->dma_mask || !dma_supported(dev, dma_mask))
|
|
return -EIO;
|
|
|
|
*dev->dma_mask = dma_mask;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define PREALLOC_DMA_DEBUG_ENTRIES 4096
|
|
|
|
static int __init dma_debug_do_init(void)
|
|
{
|
|
dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
|
|
return 0;
|
|
}
|
|
fs_initcall(dma_debug_do_init);
|
|
|
|
#ifdef CONFIG_ARM_DMA_USE_IOMMU
|
|
|
|
/* IOMMU */
|
|
|
|
static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
|
|
size_t size)
|
|
{
|
|
unsigned int order = get_order(size);
|
|
unsigned int align = 0;
|
|
unsigned int count, start;
|
|
unsigned long flags;
|
|
|
|
if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
|
|
order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
|
|
|
|
count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
|
|
(1 << mapping->order) - 1) >> mapping->order;
|
|
|
|
if (order > mapping->order)
|
|
align = (1 << (order - mapping->order)) - 1;
|
|
|
|
spin_lock_irqsave(&mapping->lock, flags);
|
|
start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
|
|
count, align);
|
|
if (start > mapping->bits) {
|
|
spin_unlock_irqrestore(&mapping->lock, flags);
|
|
return DMA_ERROR_CODE;
|
|
}
|
|
|
|
bitmap_set(mapping->bitmap, start, count);
|
|
spin_unlock_irqrestore(&mapping->lock, flags);
|
|
|
|
return mapping->base + (start << (mapping->order + PAGE_SHIFT));
|
|
}
|
|
|
|
static inline void __free_iova(struct dma_iommu_mapping *mapping,
|
|
dma_addr_t addr, size_t size)
|
|
{
|
|
unsigned int start = (addr - mapping->base) >>
|
|
(mapping->order + PAGE_SHIFT);
|
|
unsigned int count = ((size >> PAGE_SHIFT) +
|
|
(1 << mapping->order) - 1) >> mapping->order;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&mapping->lock, flags);
|
|
bitmap_clear(mapping->bitmap, start, count);
|
|
spin_unlock_irqrestore(&mapping->lock, flags);
|
|
}
|
|
|
|
static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
|
|
gfp_t gfp, struct dma_attrs *attrs)
|
|
{
|
|
struct page **pages;
|
|
int count = size >> PAGE_SHIFT;
|
|
int array_size = count * sizeof(struct page *);
|
|
int i = 0;
|
|
|
|
if (array_size <= PAGE_SIZE)
|
|
pages = kzalloc(array_size, gfp);
|
|
else
|
|
pages = vzalloc(array_size);
|
|
if (!pages)
|
|
return NULL;
|
|
|
|
if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
|
|
{
|
|
unsigned long order = get_order(size);
|
|
struct page *page;
|
|
|
|
page = dma_alloc_from_contiguous(dev, count, order);
|
|
if (!page)
|
|
goto error;
|
|
|
|
__dma_clear_buffer(page, size);
|
|
|
|
for (i = 0; i < count; i++)
|
|
pages[i] = page + i;
|
|
|
|
return pages;
|
|
}
|
|
|
|
/*
|
|
* IOMMU can map any pages, so himem can also be used here
|
|
*/
|
|
gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
|
|
|
|
while (count) {
|
|
int j, order = __fls(count);
|
|
|
|
pages[i] = alloc_pages(gfp, order);
|
|
while (!pages[i] && order)
|
|
pages[i] = alloc_pages(gfp, --order);
|
|
if (!pages[i])
|
|
goto error;
|
|
|
|
if (order) {
|
|
split_page(pages[i], order);
|
|
j = 1 << order;
|
|
while (--j)
|
|
pages[i + j] = pages[i] + j;
|
|
}
|
|
|
|
__dma_clear_buffer(pages[i], PAGE_SIZE << order);
|
|
i += 1 << order;
|
|
count -= 1 << order;
|
|
}
|
|
|
|
return pages;
|
|
error:
|
|
while (i--)
|
|
if (pages[i])
|
|
__free_pages(pages[i], 0);
|
|
if (array_size <= PAGE_SIZE)
|
|
kfree(pages);
|
|
else
|
|
vfree(pages);
|
|
return NULL;
|
|
}
|
|
|
|
static int __iommu_free_buffer(struct device *dev, struct page **pages,
|
|
size_t size, struct dma_attrs *attrs)
|
|
{
|
|
int count = size >> PAGE_SHIFT;
|
|
int array_size = count * sizeof(struct page *);
|
|
int i;
|
|
|
|
if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
|
|
dma_release_from_contiguous(dev, pages[0], count);
|
|
} else {
|
|
for (i = 0; i < count; i++)
|
|
if (pages[i])
|
|
__free_pages(pages[i], 0);
|
|
}
|
|
|
|
if (array_size <= PAGE_SIZE)
|
|
kfree(pages);
|
|
else
|
|
vfree(pages);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Create a CPU mapping for a specified pages
|
|
*/
|
|
static void *
|
|
__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
|
|
const void *caller)
|
|
{
|
|
unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
|
struct vm_struct *area;
|
|
unsigned long p;
|
|
|
|
area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
|
|
caller);
|
|
if (!area)
|
|
return NULL;
|
|
|
|
area->pages = pages;
|
|
area->nr_pages = nr_pages;
|
|
p = (unsigned long)area->addr;
|
|
|
|
for (i = 0; i < nr_pages; i++) {
|
|
phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
|
|
if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
|
|
goto err;
|
|
p += PAGE_SIZE;
|
|
}
|
|
return area->addr;
|
|
err:
|
|
unmap_kernel_range((unsigned long)area->addr, size);
|
|
vunmap(area->addr);
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Create a mapping in device IO address space for specified pages
|
|
*/
|
|
static dma_addr_t
|
|
__iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
|
|
{
|
|
struct dma_iommu_mapping *mapping = dev->archdata.mapping;
|
|
unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
|
dma_addr_t dma_addr, iova;
|
|
int i, ret = DMA_ERROR_CODE;
|
|
|
|
dma_addr = __alloc_iova(mapping, size);
|
|
if (dma_addr == DMA_ERROR_CODE)
|
|
return dma_addr;
|
|
|
|
iova = dma_addr;
|
|
for (i = 0; i < count; ) {
|
|
unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
|
|
phys_addr_t phys = page_to_phys(pages[i]);
|
|
unsigned int len, j;
|
|
|
|
for (j = i + 1; j < count; j++, next_pfn++)
|
|
if (page_to_pfn(pages[j]) != next_pfn)
|
|
break;
|
|
|
|
len = (j - i) << PAGE_SHIFT;
|
|
ret = iommu_map(mapping->domain, iova, phys, len,
|
|
IOMMU_READ|IOMMU_WRITE);
|
|
if (ret < 0)
|
|
goto fail;
|
|
iova += len;
|
|
i = j;
|
|
}
|
|
return dma_addr;
|
|
fail:
|
|
iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
|
|
__free_iova(mapping, dma_addr, size);
|
|
return DMA_ERROR_CODE;
|
|
}
|
|
|
|
static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
|
|
{
|
|
struct dma_iommu_mapping *mapping = dev->archdata.mapping;
|
|
|
|
/*
|
|
* add optional in-page offset from iova to size and align
|
|
* result to page size
|
|
*/
|
|
size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
|
|
iova &= PAGE_MASK;
|
|
|
|
iommu_unmap(mapping->domain, iova, size);
|
|
__free_iova(mapping, iova, size);
|
|
return 0;
|
|
}
|
|
|
|
static struct page **__atomic_get_pages(void *addr)
|
|
{
|
|
struct dma_pool *pool = &atomic_pool;
|
|
struct page **pages = pool->pages;
|
|
int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
|
|
|
|
return pages + offs;
|
|
}
|
|
|
|
static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
|
|
{
|
|
struct vm_struct *area;
|
|
|
|
if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
|
|
return __atomic_get_pages(cpu_addr);
|
|
|
|
if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
|
|
return cpu_addr;
|
|
|
|
area = find_vm_area(cpu_addr);
|
|
if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
|
|
return area->pages;
|
|
return NULL;
|
|
}
|
|
|
|
static void *__iommu_alloc_atomic(struct device *dev, size_t size,
|
|
dma_addr_t *handle)
|
|
{
|
|
struct page *page;
|
|
void *addr;
|
|
|
|
addr = __alloc_from_pool(size, &page);
|
|
if (!addr)
|
|
return NULL;
|
|
|
|
*handle = __iommu_create_mapping(dev, &page, size);
|
|
if (*handle == DMA_ERROR_CODE)
|
|
goto err_mapping;
|
|
|
|
return addr;
|
|
|
|
err_mapping:
|
|
__free_from_pool(addr, size);
|
|
return NULL;
|
|
}
|
|
|
|
static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
|
|
dma_addr_t handle, size_t size)
|
|
{
|
|
__iommu_remove_mapping(dev, handle, size);
|
|
__free_from_pool(cpu_addr, size);
|
|
}
|
|
|
|
static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
|
|
dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
|
|
{
|
|
pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
|
|
struct page **pages;
|
|
void *addr = NULL;
|
|
|
|
*handle = DMA_ERROR_CODE;
|
|
size = PAGE_ALIGN(size);
|
|
|
|
if (gfp & GFP_ATOMIC)
|
|
return __iommu_alloc_atomic(dev, size, handle);
|
|
|
|
/*
|
|
* Following is a work-around (a.k.a. hack) to prevent pages
|
|
* with __GFP_COMP being passed to split_page() which cannot
|
|
* handle them. The real problem is that this flag probably
|
|
* should be 0 on ARM as it is not supported on this
|
|
* platform; see CONFIG_HUGETLBFS.
|
|
*/
|
|
gfp &= ~(__GFP_COMP);
|
|
|
|
pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
|
|
if (!pages)
|
|
return NULL;
|
|
|
|
*handle = __iommu_create_mapping(dev, pages, size);
|
|
if (*handle == DMA_ERROR_CODE)
|
|
goto err_buffer;
|
|
|
|
if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
|
|
return pages;
|
|
|
|
addr = __iommu_alloc_remap(pages, size, gfp, prot,
|
|
__builtin_return_address(0));
|
|
if (!addr)
|
|
goto err_mapping;
|
|
|
|
return addr;
|
|
|
|
err_mapping:
|
|
__iommu_remove_mapping(dev, *handle, size);
|
|
err_buffer:
|
|
__iommu_free_buffer(dev, pages, size, attrs);
|
|
return NULL;
|
|
}
|
|
|
|
static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
|
|
void *cpu_addr, dma_addr_t dma_addr, size_t size,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
unsigned long uaddr = vma->vm_start;
|
|
unsigned long usize = vma->vm_end - vma->vm_start;
|
|
struct page **pages = __iommu_get_pages(cpu_addr, attrs);
|
|
|
|
vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
|
|
|
|
if (!pages)
|
|
return -ENXIO;
|
|
|
|
do {
|
|
int ret = vm_insert_page(vma, uaddr, *pages++);
|
|
if (ret) {
|
|
pr_err("Remapping memory failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
uaddr += PAGE_SIZE;
|
|
usize -= PAGE_SIZE;
|
|
} while (usize > 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* free a page as defined by the above mapping.
|
|
* Must not be called with IRQs disabled.
|
|
*/
|
|
void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
|
|
dma_addr_t handle, struct dma_attrs *attrs)
|
|
{
|
|
struct page **pages;
|
|
size = PAGE_ALIGN(size);
|
|
|
|
if (__in_atomic_pool(cpu_addr, size)) {
|
|
__iommu_free_atomic(dev, cpu_addr, handle, size);
|
|
return;
|
|
}
|
|
|
|
pages = __iommu_get_pages(cpu_addr, attrs);
|
|
if (!pages) {
|
|
WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
|
|
return;
|
|
}
|
|
|
|
if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
|
|
unmap_kernel_range((unsigned long)cpu_addr, size);
|
|
vunmap(cpu_addr);
|
|
}
|
|
|
|
__iommu_remove_mapping(dev, handle, size);
|
|
__iommu_free_buffer(dev, pages, size, attrs);
|
|
}
|
|
|
|
static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
|
|
void *cpu_addr, dma_addr_t dma_addr,
|
|
size_t size, struct dma_attrs *attrs)
|
|
{
|
|
unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
|
struct page **pages = __iommu_get_pages(cpu_addr, attrs);
|
|
|
|
if (!pages)
|
|
return -ENXIO;
|
|
|
|
return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
|
|
GFP_KERNEL);
|
|
}
|
|
|
|
static int __dma_direction_to_prot(enum dma_data_direction dir)
|
|
{
|
|
int prot;
|
|
|
|
switch (dir) {
|
|
case DMA_BIDIRECTIONAL:
|
|
prot = IOMMU_READ | IOMMU_WRITE;
|
|
break;
|
|
case DMA_TO_DEVICE:
|
|
prot = IOMMU_READ;
|
|
break;
|
|
case DMA_FROM_DEVICE:
|
|
prot = IOMMU_WRITE;
|
|
break;
|
|
default:
|
|
prot = 0;
|
|
}
|
|
|
|
return prot;
|
|
}
|
|
|
|
/*
|
|
* Map a part of the scatter-gather list into contiguous io address space
|
|
*/
|
|
static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
|
|
size_t size, dma_addr_t *handle,
|
|
enum dma_data_direction dir, struct dma_attrs *attrs,
|
|
bool is_coherent)
|
|
{
|
|
struct dma_iommu_mapping *mapping = dev->archdata.mapping;
|
|
dma_addr_t iova, iova_base;
|
|
int ret = 0;
|
|
unsigned int count;
|
|
struct scatterlist *s;
|
|
int prot;
|
|
|
|
size = PAGE_ALIGN(size);
|
|
*handle = DMA_ERROR_CODE;
|
|
|
|
iova_base = iova = __alloc_iova(mapping, size);
|
|
if (iova == DMA_ERROR_CODE)
|
|
return -ENOMEM;
|
|
|
|
for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
|
|
phys_addr_t phys = page_to_phys(sg_page(s));
|
|
unsigned int len = PAGE_ALIGN(s->offset + s->length);
|
|
|
|
if (!is_coherent &&
|
|
!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
|
|
__dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
|
|
|
|
prot = __dma_direction_to_prot(dir);
|
|
|
|
ret = iommu_map(mapping->domain, iova, phys, len, prot);
|
|
if (ret < 0)
|
|
goto fail;
|
|
count += len >> PAGE_SHIFT;
|
|
iova += len;
|
|
}
|
|
*handle = iova_base;
|
|
|
|
return 0;
|
|
fail:
|
|
iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
|
|
__free_iova(mapping, iova_base, size);
|
|
return ret;
|
|
}
|
|
|
|
static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
|
|
enum dma_data_direction dir, struct dma_attrs *attrs,
|
|
bool is_coherent)
|
|
{
|
|
struct scatterlist *s = sg, *dma = sg, *start = sg;
|
|
int i, count = 0;
|
|
unsigned int offset = s->offset;
|
|
unsigned int size = s->offset + s->length;
|
|
unsigned int max = dma_get_max_seg_size(dev);
|
|
|
|
for (i = 1; i < nents; i++) {
|
|
s = sg_next(s);
|
|
|
|
s->dma_address = DMA_ERROR_CODE;
|
|
s->dma_length = 0;
|
|
|
|
if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
|
|
if (__map_sg_chunk(dev, start, size, &dma->dma_address,
|
|
dir, attrs, is_coherent) < 0)
|
|
goto bad_mapping;
|
|
|
|
dma->dma_address += offset;
|
|
dma->dma_length = size - offset;
|
|
|
|
size = offset = s->offset;
|
|
start = s;
|
|
dma = sg_next(dma);
|
|
count += 1;
|
|
}
|
|
size += s->length;
|
|
}
|
|
if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
|
|
is_coherent) < 0)
|
|
goto bad_mapping;
|
|
|
|
dma->dma_address += offset;
|
|
dma->dma_length = size - offset;
|
|
|
|
return count+1;
|
|
|
|
bad_mapping:
|
|
for_each_sg(sg, s, count, i)
|
|
__iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
|
|
* @dev: valid struct device pointer
|
|
* @sg: list of buffers
|
|
* @nents: number of buffers to map
|
|
* @dir: DMA transfer direction
|
|
*
|
|
* Map a set of i/o coherent buffers described by scatterlist in streaming
|
|
* mode for DMA. The scatter gather list elements are merged together (if
|
|
* possible) and tagged with the appropriate dma address and length. They are
|
|
* obtained via sg_dma_{address,length}.
|
|
*/
|
|
int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
|
|
int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
|
|
{
|
|
return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
|
|
}
|
|
|
|
/**
|
|
* arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
|
|
* @dev: valid struct device pointer
|
|
* @sg: list of buffers
|
|
* @nents: number of buffers to map
|
|
* @dir: DMA transfer direction
|
|
*
|
|
* Map a set of buffers described by scatterlist in streaming mode for DMA.
|
|
* The scatter gather list elements are merged together (if possible) and
|
|
* tagged with the appropriate dma address and length. They are obtained via
|
|
* sg_dma_{address,length}.
|
|
*/
|
|
int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
|
|
int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
|
|
{
|
|
return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
|
|
}
|
|
|
|
static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
|
|
int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
|
|
bool is_coherent)
|
|
{
|
|
struct scatterlist *s;
|
|
int i;
|
|
|
|
for_each_sg(sg, s, nents, i) {
|
|
if (sg_dma_len(s))
|
|
__iommu_remove_mapping(dev, sg_dma_address(s),
|
|
sg_dma_len(s));
|
|
if (!is_coherent &&
|
|
!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
|
|
__dma_page_dev_to_cpu(sg_page(s), s->offset,
|
|
s->length, dir);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
|
|
* @dev: valid struct device pointer
|
|
* @sg: list of buffers
|
|
* @nents: number of buffers to unmap (same as was passed to dma_map_sg)
|
|
* @dir: DMA transfer direction (same as was passed to dma_map_sg)
|
|
*
|
|
* Unmap a set of streaming mode DMA translations. Again, CPU access
|
|
* rules concerning calls here are the same as for dma_unmap_single().
|
|
*/
|
|
void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
|
|
int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
|
|
{
|
|
__iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
|
|
}
|
|
|
|
/**
|
|
* arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
|
|
* @dev: valid struct device pointer
|
|
* @sg: list of buffers
|
|
* @nents: number of buffers to unmap (same as was passed to dma_map_sg)
|
|
* @dir: DMA transfer direction (same as was passed to dma_map_sg)
|
|
*
|
|
* Unmap a set of streaming mode DMA translations. Again, CPU access
|
|
* rules concerning calls here are the same as for dma_unmap_single().
|
|
*/
|
|
void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
|
|
enum dma_data_direction dir, struct dma_attrs *attrs)
|
|
{
|
|
__iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
|
|
}
|
|
|
|
/**
|
|
* arm_iommu_sync_sg_for_cpu
|
|
* @dev: valid struct device pointer
|
|
* @sg: list of buffers
|
|
* @nents: number of buffers to map (returned from dma_map_sg)
|
|
* @dir: DMA transfer direction (same as was passed to dma_map_sg)
|
|
*/
|
|
void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
|
|
int nents, enum dma_data_direction dir)
|
|
{
|
|
struct scatterlist *s;
|
|
int i;
|
|
|
|
for_each_sg(sg, s, nents, i)
|
|
__dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
|
|
|
|
}
|
|
|
|
/**
|
|
* arm_iommu_sync_sg_for_device
|
|
* @dev: valid struct device pointer
|
|
* @sg: list of buffers
|
|
* @nents: number of buffers to map (returned from dma_map_sg)
|
|
* @dir: DMA transfer direction (same as was passed to dma_map_sg)
|
|
*/
|
|
void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
|
|
int nents, enum dma_data_direction dir)
|
|
{
|
|
struct scatterlist *s;
|
|
int i;
|
|
|
|
for_each_sg(sg, s, nents, i)
|
|
__dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
|
|
}
|
|
|
|
|
|
/**
|
|
* arm_coherent_iommu_map_page
|
|
* @dev: valid struct device pointer
|
|
* @page: page that buffer resides in
|
|
* @offset: offset into page for start of buffer
|
|
* @size: size of buffer to map
|
|
* @dir: DMA transfer direction
|
|
*
|
|
* Coherent IOMMU aware version of arm_dma_map_page()
|
|
*/
|
|
static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
|
|
unsigned long offset, size_t size, enum dma_data_direction dir,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
struct dma_iommu_mapping *mapping = dev->archdata.mapping;
|
|
dma_addr_t dma_addr;
|
|
int ret, prot, len = PAGE_ALIGN(size + offset);
|
|
|
|
dma_addr = __alloc_iova(mapping, len);
|
|
if (dma_addr == DMA_ERROR_CODE)
|
|
return dma_addr;
|
|
|
|
prot = __dma_direction_to_prot(dir);
|
|
|
|
ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
|
|
if (ret < 0)
|
|
goto fail;
|
|
|
|
return dma_addr + offset;
|
|
fail:
|
|
__free_iova(mapping, dma_addr, len);
|
|
return DMA_ERROR_CODE;
|
|
}
|
|
|
|
/**
|
|
* arm_iommu_map_page
|
|
* @dev: valid struct device pointer
|
|
* @page: page that buffer resides in
|
|
* @offset: offset into page for start of buffer
|
|
* @size: size of buffer to map
|
|
* @dir: DMA transfer direction
|
|
*
|
|
* IOMMU aware version of arm_dma_map_page()
|
|
*/
|
|
static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
|
|
unsigned long offset, size_t size, enum dma_data_direction dir,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
|
|
__dma_page_cpu_to_dev(page, offset, size, dir);
|
|
|
|
return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
|
|
}
|
|
|
|
/**
|
|
* arm_coherent_iommu_unmap_page
|
|
* @dev: valid struct device pointer
|
|
* @handle: DMA address of buffer
|
|
* @size: size of buffer (same as passed to dma_map_page)
|
|
* @dir: DMA transfer direction (same as passed to dma_map_page)
|
|
*
|
|
* Coherent IOMMU aware version of arm_dma_unmap_page()
|
|
*/
|
|
static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
|
|
size_t size, enum dma_data_direction dir,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
struct dma_iommu_mapping *mapping = dev->archdata.mapping;
|
|
dma_addr_t iova = handle & PAGE_MASK;
|
|
int offset = handle & ~PAGE_MASK;
|
|
int len = PAGE_ALIGN(size + offset);
|
|
|
|
if (!iova)
|
|
return;
|
|
|
|
iommu_unmap(mapping->domain, iova, len);
|
|
__free_iova(mapping, iova, len);
|
|
}
|
|
|
|
/**
|
|
* arm_iommu_unmap_page
|
|
* @dev: valid struct device pointer
|
|
* @handle: DMA address of buffer
|
|
* @size: size of buffer (same as passed to dma_map_page)
|
|
* @dir: DMA transfer direction (same as passed to dma_map_page)
|
|
*
|
|
* IOMMU aware version of arm_dma_unmap_page()
|
|
*/
|
|
static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
|
|
size_t size, enum dma_data_direction dir,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
struct dma_iommu_mapping *mapping = dev->archdata.mapping;
|
|
dma_addr_t iova = handle & PAGE_MASK;
|
|
struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
|
|
int offset = handle & ~PAGE_MASK;
|
|
int len = PAGE_ALIGN(size + offset);
|
|
|
|
if (!iova)
|
|
return;
|
|
|
|
if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
|
|
__dma_page_dev_to_cpu(page, offset, size, dir);
|
|
|
|
iommu_unmap(mapping->domain, iova, len);
|
|
__free_iova(mapping, iova, len);
|
|
}
|
|
|
|
static void arm_iommu_sync_single_for_cpu(struct device *dev,
|
|
dma_addr_t handle, size_t size, enum dma_data_direction dir)
|
|
{
|
|
struct dma_iommu_mapping *mapping = dev->archdata.mapping;
|
|
dma_addr_t iova = handle & PAGE_MASK;
|
|
struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
|
|
unsigned int offset = handle & ~PAGE_MASK;
|
|
|
|
if (!iova)
|
|
return;
|
|
|
|
__dma_page_dev_to_cpu(page, offset, size, dir);
|
|
}
|
|
|
|
static void arm_iommu_sync_single_for_device(struct device *dev,
|
|
dma_addr_t handle, size_t size, enum dma_data_direction dir)
|
|
{
|
|
struct dma_iommu_mapping *mapping = dev->archdata.mapping;
|
|
dma_addr_t iova = handle & PAGE_MASK;
|
|
struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
|
|
unsigned int offset = handle & ~PAGE_MASK;
|
|
|
|
if (!iova)
|
|
return;
|
|
|
|
__dma_page_cpu_to_dev(page, offset, size, dir);
|
|
}
|
|
|
|
struct dma_map_ops iommu_ops = {
|
|
.alloc = arm_iommu_alloc_attrs,
|
|
.free = arm_iommu_free_attrs,
|
|
.mmap = arm_iommu_mmap_attrs,
|
|
.get_sgtable = arm_iommu_get_sgtable,
|
|
|
|
.map_page = arm_iommu_map_page,
|
|
.unmap_page = arm_iommu_unmap_page,
|
|
.sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
|
|
.sync_single_for_device = arm_iommu_sync_single_for_device,
|
|
|
|
.map_sg = arm_iommu_map_sg,
|
|
.unmap_sg = arm_iommu_unmap_sg,
|
|
.sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
|
|
.sync_sg_for_device = arm_iommu_sync_sg_for_device,
|
|
|
|
.set_dma_mask = arm_dma_set_mask,
|
|
};
|
|
|
|
struct dma_map_ops iommu_coherent_ops = {
|
|
.alloc = arm_iommu_alloc_attrs,
|
|
.free = arm_iommu_free_attrs,
|
|
.mmap = arm_iommu_mmap_attrs,
|
|
.get_sgtable = arm_iommu_get_sgtable,
|
|
|
|
.map_page = arm_coherent_iommu_map_page,
|
|
.unmap_page = arm_coherent_iommu_unmap_page,
|
|
|
|
.map_sg = arm_coherent_iommu_map_sg,
|
|
.unmap_sg = arm_coherent_iommu_unmap_sg,
|
|
|
|
.set_dma_mask = arm_dma_set_mask,
|
|
};
|
|
|
|
/**
|
|
* arm_iommu_create_mapping
|
|
* @bus: pointer to the bus holding the client device (for IOMMU calls)
|
|
* @base: start address of the valid IO address space
|
|
* @size: size of the valid IO address space
|
|
* @order: accuracy of the IO addresses allocations
|
|
*
|
|
* Creates a mapping structure which holds information about used/unused
|
|
* IO address ranges, which is required to perform memory allocation and
|
|
* mapping with IOMMU aware functions.
|
|
*
|
|
* The client device need to be attached to the mapping with
|
|
* arm_iommu_attach_device function.
|
|
*/
|
|
struct dma_iommu_mapping *
|
|
arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
|
|
int order)
|
|
{
|
|
unsigned int count = size >> (PAGE_SHIFT + order);
|
|
unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
|
|
struct dma_iommu_mapping *mapping;
|
|
int err = -ENOMEM;
|
|
|
|
if (!count)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
|
|
if (!mapping)
|
|
goto err;
|
|
|
|
mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
|
|
if (!mapping->bitmap)
|
|
goto err2;
|
|
|
|
mapping->base = base;
|
|
mapping->bits = BITS_PER_BYTE * bitmap_size;
|
|
mapping->order = order;
|
|
spin_lock_init(&mapping->lock);
|
|
|
|
mapping->domain = iommu_domain_alloc(bus);
|
|
if (!mapping->domain)
|
|
goto err3;
|
|
|
|
kref_init(&mapping->kref);
|
|
return mapping;
|
|
err3:
|
|
kfree(mapping->bitmap);
|
|
err2:
|
|
kfree(mapping);
|
|
err:
|
|
return ERR_PTR(err);
|
|
}
|
|
EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
|
|
|
|
static void release_iommu_mapping(struct kref *kref)
|
|
{
|
|
struct dma_iommu_mapping *mapping =
|
|
container_of(kref, struct dma_iommu_mapping, kref);
|
|
|
|
iommu_domain_free(mapping->domain);
|
|
kfree(mapping->bitmap);
|
|
kfree(mapping);
|
|
}
|
|
|
|
void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
|
|
{
|
|
if (mapping)
|
|
kref_put(&mapping->kref, release_iommu_mapping);
|
|
}
|
|
EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
|
|
|
|
/**
|
|
* arm_iommu_attach_device
|
|
* @dev: valid struct device pointer
|
|
* @mapping: io address space mapping structure (returned from
|
|
* arm_iommu_create_mapping)
|
|
*
|
|
* Attaches specified io address space mapping to the provided device,
|
|
* this replaces the dma operations (dma_map_ops pointer) with the
|
|
* IOMMU aware version. More than one client might be attached to
|
|
* the same io address space mapping.
|
|
*/
|
|
int arm_iommu_attach_device(struct device *dev,
|
|
struct dma_iommu_mapping *mapping)
|
|
{
|
|
int err;
|
|
|
|
err = iommu_attach_device(mapping->domain, dev);
|
|
if (err)
|
|
return err;
|
|
|
|
kref_get(&mapping->kref);
|
|
dev->archdata.mapping = mapping;
|
|
set_dma_ops(dev, &iommu_ops);
|
|
|
|
pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
|
|
|
|
/**
|
|
* arm_iommu_detach_device
|
|
* @dev: valid struct device pointer
|
|
*
|
|
* Detaches the provided device from a previously attached map.
|
|
* This voids the dma operations (dma_map_ops pointer)
|
|
*/
|
|
void arm_iommu_detach_device(struct device *dev)
|
|
{
|
|
struct dma_iommu_mapping *mapping;
|
|
|
|
mapping = to_dma_iommu_mapping(dev);
|
|
if (!mapping) {
|
|
dev_warn(dev, "Not attached\n");
|
|
return;
|
|
}
|
|
|
|
iommu_detach_device(mapping->domain, dev);
|
|
kref_put(&mapping->kref, release_iommu_mapping);
|
|
dev->archdata.mapping = NULL;
|
|
set_dma_ops(dev, NULL);
|
|
|
|
pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
|
|
}
|
|
EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
|
|
|
|
#endif
|