![Steven Capper](/assets/img/avatar_default.png)
When given a compound high page, __flush_dcache_page will only flush
the first page of the compound page repeatedly rather than the entire
set of constituent pages.
This error was introduced by:
0b19f93
ARM: mm: Add support for flushing HugeTLB pages.
This patch corrects the logic such that all constituent pages are now
flushed.
Cc: stable@vger.kernel.org # 3.10+
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
380 lines
9.7 KiB
C
380 lines
9.7 KiB
C
/*
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* linux/arch/arm/mm/flush.c
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*
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* Copyright (C) 1995-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/pagemap.h>
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#include <linux/highmem.h>
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#include <asm/cacheflush.h>
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#include <asm/cachetype.h>
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#include <asm/highmem.h>
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#include <asm/smp_plat.h>
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#include <asm/tlbflush.h>
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#include <linux/hugetlb.h>
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#include "mm.h"
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#ifdef CONFIG_CPU_CACHE_VIPT
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static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
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{
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unsigned long to = FLUSH_ALIAS_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
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const int zero = 0;
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set_top_pte(to, pfn_pte(pfn, PAGE_KERNEL));
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asm( "mcrr p15, 0, %1, %0, c14\n"
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" mcr p15, 0, %2, c7, c10, 4"
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:
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: "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
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: "cc");
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}
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static void flush_icache_alias(unsigned long pfn, unsigned long vaddr, unsigned long len)
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{
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unsigned long va = FLUSH_ALIAS_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
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unsigned long offset = vaddr & (PAGE_SIZE - 1);
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unsigned long to;
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set_top_pte(va, pfn_pte(pfn, PAGE_KERNEL));
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to = va + offset;
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flush_icache_range(to, to + len);
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}
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void flush_cache_mm(struct mm_struct *mm)
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{
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if (cache_is_vivt()) {
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vivt_flush_cache_mm(mm);
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return;
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}
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if (cache_is_vipt_aliasing()) {
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asm( "mcr p15, 0, %0, c7, c14, 0\n"
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" mcr p15, 0, %0, c7, c10, 4"
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:
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: "r" (0)
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: "cc");
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}
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}
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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{
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if (cache_is_vivt()) {
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vivt_flush_cache_range(vma, start, end);
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return;
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}
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if (cache_is_vipt_aliasing()) {
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asm( "mcr p15, 0, %0, c7, c14, 0\n"
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" mcr p15, 0, %0, c7, c10, 4"
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:
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: "r" (0)
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: "cc");
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}
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if (vma->vm_flags & VM_EXEC)
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__flush_icache_all();
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}
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void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
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{
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if (cache_is_vivt()) {
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vivt_flush_cache_page(vma, user_addr, pfn);
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return;
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}
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if (cache_is_vipt_aliasing()) {
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flush_pfn_alias(pfn, user_addr);
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__flush_icache_all();
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}
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if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
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__flush_icache_all();
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}
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#else
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#define flush_pfn_alias(pfn,vaddr) do { } while (0)
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#define flush_icache_alias(pfn,vaddr,len) do { } while (0)
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#endif
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static void flush_ptrace_access_other(void *args)
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{
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__flush_icache_all();
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}
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static
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void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
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unsigned long uaddr, void *kaddr, unsigned long len)
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{
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if (cache_is_vivt()) {
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if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
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unsigned long addr = (unsigned long)kaddr;
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__cpuc_coherent_kern_range(addr, addr + len);
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}
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return;
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}
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if (cache_is_vipt_aliasing()) {
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flush_pfn_alias(page_to_pfn(page), uaddr);
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__flush_icache_all();
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return;
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}
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/* VIPT non-aliasing D-cache */
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if (vma->vm_flags & VM_EXEC) {
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unsigned long addr = (unsigned long)kaddr;
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if (icache_is_vipt_aliasing())
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flush_icache_alias(page_to_pfn(page), uaddr, len);
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else
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__cpuc_coherent_kern_range(addr, addr + len);
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if (cache_ops_need_broadcast())
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smp_call_function(flush_ptrace_access_other,
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NULL, 1);
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}
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}
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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* space" model to handle this.
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*
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* Note that this code needs to run on the current CPU.
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*/
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long uaddr, void *dst, const void *src,
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unsigned long len)
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{
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#ifdef CONFIG_SMP
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preempt_disable();
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#endif
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memcpy(dst, src, len);
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flush_ptrace_access(vma, page, uaddr, dst, len);
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#ifdef CONFIG_SMP
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preempt_enable();
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#endif
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}
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void __flush_dcache_page(struct address_space *mapping, struct page *page)
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{
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/*
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* Writeback any data associated with the kernel mapping of this
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* page. This ensures that data in the physical page is mutually
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* coherent with the kernels mapping.
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*/
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if (!PageHighMem(page)) {
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size_t page_size = PAGE_SIZE << compound_order(page);
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__cpuc_flush_dcache_area(page_address(page), page_size);
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} else {
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unsigned long i;
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if (cache_is_vipt_nonaliasing()) {
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for (i = 0; i < (1 << compound_order(page)); i++) {
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void *addr = kmap_atomic(page + i);
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__cpuc_flush_dcache_area(addr, PAGE_SIZE);
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kunmap_atomic(addr);
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}
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} else {
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for (i = 0; i < (1 << compound_order(page)); i++) {
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void *addr = kmap_high_get(page + i);
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if (addr) {
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__cpuc_flush_dcache_area(addr, PAGE_SIZE);
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kunmap_high(page + i);
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}
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}
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}
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}
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/*
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* If this is a page cache page, and we have an aliasing VIPT cache,
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* we only need to do one flush - which would be at the relevant
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* userspace colour, which is congruent with page->index.
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*/
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if (mapping && cache_is_vipt_aliasing())
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flush_pfn_alias(page_to_pfn(page),
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page->index << PAGE_CACHE_SHIFT);
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}
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static void __flush_dcache_aliases(struct address_space *mapping, struct page *page)
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{
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struct mm_struct *mm = current->active_mm;
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struct vm_area_struct *mpnt;
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pgoff_t pgoff;
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/*
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* There are possible user space mappings of this page:
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* - VIVT cache: we need to also write back and invalidate all user
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* data in the current VM view associated with this page.
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* - aliasing VIPT: we only need to find one mapping of this page.
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*/
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pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
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flush_dcache_mmap_lock(mapping);
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vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
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unsigned long offset;
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/*
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* If this VMA is not in our MM, we can ignore it.
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*/
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if (mpnt->vm_mm != mm)
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continue;
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if (!(mpnt->vm_flags & VM_MAYSHARE))
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continue;
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offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
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flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page));
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}
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flush_dcache_mmap_unlock(mapping);
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}
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#if __LINUX_ARM_ARCH__ >= 6
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void __sync_icache_dcache(pte_t pteval)
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{
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unsigned long pfn;
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struct page *page;
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struct address_space *mapping;
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if (cache_is_vipt_nonaliasing() && !pte_exec(pteval))
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/* only flush non-aliasing VIPT caches for exec mappings */
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return;
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pfn = pte_pfn(pteval);
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if (!pfn_valid(pfn))
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return;
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page = pfn_to_page(pfn);
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if (cache_is_vipt_aliasing())
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mapping = page_mapping(page);
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else
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mapping = NULL;
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if (!test_and_set_bit(PG_dcache_clean, &page->flags))
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__flush_dcache_page(mapping, page);
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if (pte_exec(pteval))
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__flush_icache_all();
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}
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#endif
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/*
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* Ensure cache coherency between kernel mapping and userspace mapping
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* of this page.
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*
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* We have three cases to consider:
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* - VIPT non-aliasing cache: fully coherent so nothing required.
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* - VIVT: fully aliasing, so we need to handle every alias in our
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* current VM view.
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* - VIPT aliasing: need to handle one alias in our current VM view.
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*
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* If we need to handle aliasing:
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* If the page only exists in the page cache and there are no user
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* space mappings, we can be lazy and remember that we may have dirty
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* kernel cache lines for later. Otherwise, we assume we have
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* aliasing mappings.
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*
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* Note that we disable the lazy flush for SMP configurations where
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* the cache maintenance operations are not automatically broadcasted.
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*/
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping;
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/*
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* The zero page is never written to, so never has any dirty
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* cache lines, and therefore never needs to be flushed.
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*/
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if (page == ZERO_PAGE(0))
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return;
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mapping = page_mapping(page);
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if (!cache_ops_need_broadcast() &&
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mapping && !page_mapped(page))
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clear_bit(PG_dcache_clean, &page->flags);
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else {
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__flush_dcache_page(mapping, page);
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if (mapping && cache_is_vivt())
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__flush_dcache_aliases(mapping, page);
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else if (mapping)
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__flush_icache_all();
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set_bit(PG_dcache_clean, &page->flags);
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}
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}
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EXPORT_SYMBOL(flush_dcache_page);
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/*
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* Ensure cache coherency for the kernel mapping of this page. We can
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* assume that the page is pinned via kmap.
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*
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* If the page only exists in the page cache and there are no user
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* space mappings, this is a no-op since the page was already marked
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* dirty at creation. Otherwise, we need to flush the dirty kernel
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* cache lines directly.
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*/
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void flush_kernel_dcache_page(struct page *page)
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{
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if (cache_is_vivt() || cache_is_vipt_aliasing()) {
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struct address_space *mapping;
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mapping = page_mapping(page);
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if (!mapping || mapping_mapped(mapping)) {
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void *addr;
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addr = page_address(page);
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/*
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* kmap_atomic() doesn't set the page virtual
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* address for highmem pages, and
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* kunmap_atomic() takes care of cache
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* flushing already.
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*/
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if (!IS_ENABLED(CONFIG_HIGHMEM) || addr)
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__cpuc_flush_dcache_area(addr, PAGE_SIZE);
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}
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}
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}
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EXPORT_SYMBOL(flush_kernel_dcache_page);
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/*
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* Flush an anonymous page so that users of get_user_pages()
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* can safely access the data. The expected sequence is:
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*
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* get_user_pages()
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* -> flush_anon_page
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* memcpy() to/from page
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* if written to page, flush_dcache_page()
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*/
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void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
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{
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unsigned long pfn;
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/* VIPT non-aliasing caches need do nothing */
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if (cache_is_vipt_nonaliasing())
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return;
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/*
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* Write back and invalidate userspace mapping.
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*/
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pfn = page_to_pfn(page);
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if (cache_is_vivt()) {
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flush_cache_page(vma, vmaddr, pfn);
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} else {
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/*
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* For aliasing VIPT, we can flush an alias of the
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* userspace address only.
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*/
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flush_pfn_alias(pfn, vmaddr);
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__flush_icache_all();
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}
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/*
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* Invalidate kernel mapping. No data should be contained
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* in this mapping of the page. FIXME: this is overkill
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* since we actually ask for a write-back and invalidate.
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*/
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__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
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}
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